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M28W320CB100ZB6T Datasheet(PDF) 6 Page - STMicroelectronics |
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M28W320CB100ZB6T Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 42 page  M28W320CT, M28W320CB 6/42 SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A20). The address signals are inputs driven with CMOS voltage levels. They are latched during a write operation. Data Input/Output (DQ0-DQ15). The data in- puts, a word to be programmed or a command to the C.I., are latched on the Chip Enable E or Write Enable W rising edge, whichever occurs first. The data output from the memory Array, the Electronic Signature, the block protection status or Status Register is valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected, the outputs are dis- abled or RP is tied to VIL. Commands are issued on DQ0-DQ7. Chip Enable (E). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the stand-by level. E can also be used to control writing to the command register and to the memo- ry array, while W remains at VIL. Output Enable (G). The Output Enable controls the data Input/Output buffers. Write Enable (W). This input controls writing to the Command Register, Input Address and Data latches. Write Protect (WP). This input gives an addition- al hardware protection level against program or erase when pulled at VIL, as described in the Block Protection description. Reset Input (RP). The RP input provides hard- ware reset of the memory. When RP is at VIL,the memory is in reset mode: the outputs are put to High-Z and the current consumption is minimised. When RP is at VIH, the device is in normal opera- tion. Exiting reset mode the device enters read ar- ray mode. VDD Supply Voltage (2.7V to 3.6V). VDD pro- vides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). It ranges from 2.7V to 3.6V. VDDQ Supply Voltage (1.65V to VDD). VDDQ provides the power supply to the I/O pins and en- ables all Outputs to be powered independently from VDD.VDDQ can be tied to VDD or it can use a separate supply. It can be powered either from 1.65V to VDD. VPP Program Supply Voltage (12V). VPP is both a control input and a power supply pin. The two functions are selected by the voltage range ap- plied to the pin. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against program or erase, while VPP >VPP1 en- ables these functions. VPP value is only sampled at the beginning of a program or erase; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. If VPP is used in the range 11.4V to 12.6V acts as a power supply pin. In this condition VPP value must be stable until P/E algorithm is completed (see Table 24 and 25). VSS Ground. VSS is the reference for all the volt- age measurements. |
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