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SN74V263 Datasheet(PDF) 23 Page - Texas Instruments |
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SN74V263 Datasheet(HTML) 23 Page - Texas Instruments |
23 / 52 page SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1st Parallel Offset Write/Read Cycle D/Q17 Data Inputs/Outputs D/Q0 EMPTY OFFSET REGISTER X X 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Noninterspersed Parity 16 15 14 13 12 11 10 9 X 8 7 6 5 4 3 2 1 Interspersed Parity D/Q8 Number of Bits Used 2nd Parallel Offset Write/Read Cycle D/Q17 Data Inputs/Outputs D/Q0 FULL OFFSET REGISTER X X 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 X 8 7 6 5 4 3 2 1 D/Q8 SN74V263/SN74V273/SN74V283/SN74V293 ×18 Bus Width LD WEN REN SEN WCLK RCLK SN74V263, SN74V273, SN74V283, SN74V293 0 0 1 1 ↑ X Parallel write to registers: Empty offset (LSB) Empty offset (MSB) Full offset (LSB) Full offset (MSB) 0 1 0 1 X ↑ Parallel read from registers: Empty offset (LSB) Empty offset (MSB) Full offset (LSB) Full offset (MSB) ↑ ×9 TO ×9 MODE ALL OTHER MODES 0 1 1 0 ↑ X Serial shift into registers: 28 bits for the SN74V263 30 bits for the SN74V273 32 bits for the SN74V283 34 bits for the SN74V293 1 bit for each rising WCLK edge, starting with empty offset (LSB) and ending with full offset (MSB) Serial shift into registers: 26 bits for the SN74V263 28 bits for the SN74V273 30 bits for the SN74V283 32 bits for the SN74V293 1 bit for each rising WCLK edge, starting with empty offset (LSB) and ending with full offset (MSB) X 1 1 1 X X No operation 1 0 X X ↑ X Write memory 1 X 0 X X ↑ Read memory 1 1 1 X X X No operation NOTES: B. The programming method can be selected only at master reset. C. Parallel reading of the offset registers is always permitted, regardless of which programming method has been selected. D. The programming sequence applies to FWFT and standard modes. Figure 3. Programmable Flag Offset Programming Sequence (Continued) |
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