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NCP3163 Datasheet(PDF) 10 Page - ON Semiconductor |
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NCP3163 Datasheet(HTML) 10 Page - ON Semiconductor |
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10 / 20 page  NCP3163 http://onsemi.com 10 When configured for step−down or voltage−inverting applications (see application notes at the end of this document) the inductor will forward bias the output rectifier when the switch turns off. Rectifiers with a high forward voltage drop or long turn−on delay time should not be used. If the emitter is allowed to go sufficiently negative, collector current will flow, causing additional device heating and reduced conversion efficiency. Figure 12 shows that by clamping the emitter to 0.5 V, the collector current will be in the range 10 mA over temperature. A 1N5822 or equivalent Schottky barrier rectifier is recommended to fulfill these requirements. A bootstrap input is provided to reduce the output switch saturation voltage in step−down and voltage−inverting converter applications. This input is connected through a series resistor and capacitor to the switch emitter and is used to raise the internal 2.0 mA bias current source above VCC. An internal zener limits the bootstrap input voltage to VCC +7.0 V. The capacitor’s equivalent series resistance must limit the zener current to less than 100 mA. An additional series resistor may be required when using tantalum or other low ESR capacitors. The equation below is used to calculate a minimum value bootstrap capacitor based on a minimum zener voltage and an upper limit current source. CB(min) + I D t DV + 4.0 mA ton 4.0 V + 0.001 ton Parametric operation of the NCP3163 is guaranteed over a supply voltage range of 2.5 V to 40 V. When operating below 3.0 V, the Bootstrap Input should be connected to VCC. Figure 18 shows that functional operation down to 1.7 V at room temperature is possible. Package The NCP3163 is contained in a heatsinkable 16−lead plastic package in which the die is mounted on a special heat tab copper alloy pad. This pad is designed to be soldered directly to a GND connection on the printed circuit board to improve thermal conduction. Since this pad directly contacts the substrate of the die, it is important that this pad be always soldered to GND, even if surface mount heat sinking is not being used. Figure 21 shows recommended layout techniques for this package. Figure 21. Layout Guidelines to Obtain Maximum Package Power Dissipation Flare Metal for Maximum Heat Sinking 0.145 0.175 Exposed Pad 0.188 Vias to 2nd Layer Metal for Maximum Heat Sinking Minimum Recommended Exposed Copper APPLICATIONS Figures 23 through 30 show the simplicity and flexibility of the NCP3163. Three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams. Figure 22 gives the relevant design equations for the key parameters. Additionally, a complete application design aid for the NCP3163 can be found at www.onsemi.com. |
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