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M24256-BR3DW6T Datasheet(PDF) 7 Page - STMicroelectronics |
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M24256-BR3DW6T Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 19 page 7/19 M24256-B, M24128-B Figure 6. Write Mode Sequences with WC=0 (data write enabled) BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN WC PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 WC DATA IN 2 AI01106B PAGE WRITE (cont’d) WC (cont’d) DATA IN N ACK R/W ACK ACK ACK ACK ACK ACK ACK R/W ACK ACK Minimizing System Delays by Polling On ACK During the internal write cycle, the memory discon- nects itself from the bus, and copies the data from its internal latches to the memory cells. The maxi- mum write time (tw) is shown in Table 9, but the typical time is shorter. To make use of this, an Ack polling sequence can be used by the master. The sequence, as shown in Figure 7, is: – Initial condition: a Write is in progress. – Step 1: the master issues a START condition followed by a Device Select Code (the first byte of the new instruction). – Step 2: if the memory is busy with the internal write cycle, no Ack will be returned and the mas- ter goes back to Step 1. If the memory has ter- minated the internal write cycle, it responds with an Ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1). Read Operations Read operations are performed independently of the state of the WC pin. Random Address Read A dummy write is performed to load the address into the address counter, as shown in Figure 8. Then, without sending a STOP condition, the mas- ter sends another START condition, and repeats the Device Select Code, with the RW bit set to ‘1’. The memory acknowledges this, and outputs the contents of the addressed byte. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read mode, following a START condition, the master sends a Device Select Code with the RW bit set to ‘1’. The memory acknowl- edges this, and outputs the byte addressed by the |
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