M24256-BR3DW6T datasheet(7/19 Pages) STMICROELECTRONICS

Part #	M24256-BR3DW6T

Description	256/128 Kbit Serial IC Bus EEPROM With Three Chip Enable Lines

Download	19 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

Logo

7 / 19 page

7/19

M24256-B, M24128-B

Figure 6. Write Mode Sequences with WC=0 (data write enabled)

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

WC

DATA IN 2

AI01106B

PAGE WRITE

(cont’d)

WC (cont’d)

DATA IN N

ACK

R/W

ACK

R/W

ACK

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory discon-

nects itself from the bus, and copies the data from

its internal latches to the memory cells. The maxi-

mum write time (tw) is shown in Table 9, but the

typical time is shorter. To make use of this, an Ack

polling sequence can be used by the master.

The sequence, as shown in Figure 7, is:

– Initial condition: a Write is in progress.

– Step 1: the master issues a START condition

followed by a Device Select Code (the first byte

of the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no Ack will be returned and the mas-

ter goes back to Step 1. If the memory has ter-

minated the internal write cycle, it responds with

an Ack, indicating that the memory is ready to

receive the second part of the next instruction

(the first byte of this instruction having been sent

during Step 1).

Read Operations

Read operations are performed independently of

the state of the WC pin.

Random Address Read

A dummy write is performed to load the address

into the address counter, as shown in Figure 8.

Then,

without sending a STOP condition, the mas-

ter sends another START condition, and repeats

the Device Select Code, with the RW bit set to ‘1’.

The memory acknowledges this, and outputs the

contents of the addressed byte. The master must

not acknowledge the byte output, and terminates

the transfer with a STOP condition.

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read mode, following a START

condition, the master sends a Device Select Code

with the RW bit set to ‘1’. The memory acknowl-

edges this, and outputs the byte addressed by the

Similar Part No. - M24256-BR3DW6T

Manufacturer	Part #	Datasheet	Description
STMicroelectronics	M24256-BR	265Kb / 31P	512 Kbit and 256 Kbit Serial I2C bus EEPROM with three Chip Enable lines
	M24256-BR	321Kb / 35P	512 Kbit and 256 Kbit serial I짼C bus EEPROM with three Chip Enable lines
	M24256-BR	507Kb / 42P	256 Kbit serial I짼C bus EEPROM with three Chip Enable lines
	M24256-BR	415Kb / 40P	256-Kbit serial I짼C bus EEPROM
	M24256-BR	716Kb / 39P	256-Kbit serial I짼C bus EEPROM

More results

Similar Description - M24256-BR3DW6T

Manufacturer	Part #	Datasheet	Description
STMicroelectronics	M24256-BF	507Kb / 42P	256 Kbit serial I짼C bus EEPROM with three Chip Enable lines
	M24256	135Kb / 17P	256/128 Kbit Serial I짼C Bus EEPROM Without Chip Enable Lines
	M24512-W	321Kb / 35P	512 Kbit and 256 Kbit serial I짼C bus EEPROM with three Chip Enable lines
	M24512-W	265Kb / 31P	512 Kbit and 256 Kbit Serial I2C bus EEPROM with three Chip Enable lines
	M24256-A	176Kb / 20P	256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines
	M14256	111Kb / 12P	Memory Card IC 256/128 Kbit Serial I짼C Bus EEPROM
	M24128-125	290Kb / 29P	Automotive 128-Kbit serial IC bus EEPROM March 2012 Rev 1
	M24256-BW	454Kb / 25P	256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines
	M24128-DFDW6TP	1Mb / 40P	128-Kbit serial I2C bus EEPROM
	M24256-DRMN6TP	415Kb / 40P	256-Kbit serial I짼C bus EEPROM

More results

M24256-BR3DW6T Datasheet(PDF) 7 Page - STMicroelectronics

M24256-BR3DW6T Datasheet(HTML) 7 Page - STMicroelectronics

Similar Part No. - M24256-BR3DW6T

Similar Description - M24256-BR3DW6T

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Datasheet Download

Link URL