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M24256-BSMW16T Datasheet(PDF) 3 Page - STMicroelectronics |
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M24256-BSMW16T Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 19 page 3/19 M24256-B, M24128-B set (POR) circuit is included. The internal reset is held active until the VCC voltage has reached the POR threshold value, and all operations are dis- abled – the device will not respond to any com- mand. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slow- er clock, the master must have an open drain out- put, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro- nization is not employed, and so the pull-up resis- tor is not necessary, provided that the master has a push-pull (rather than open drain) output. Serial Data (SDA) The SDA pin is bi-directional, and is used to trans- fer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E2, E1, E0) These chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied directly to VCC or VSS to establish the device select code. When uncon- nected, the E2, E1 and E0 inputs are internally read as VIL (see Table 7 and Table 8) Write Control (WC) The hardware Write Control pin (WC) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC=VIL) or disable (WC=VIH) write instructions to the entire memory area. When unconnected, the WC input is internally read as VIL, and write operations are allowed. When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowl- edged. Please see the Application Note AN404 for a more detailed description of the Write Control feature. DEVICE OPERATION The memory device supports the I 2C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note AN1001. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communica- tion. Start Condition START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device con- tinuously monitors (except during a programming Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I 2C Bus AI01665 VCC CBUS SDA RL MASTER RL SCL CBUS 100 0 4 8 12 16 20 CBUS (pF) 10 1000 fc = 400kHz fc = 100kHz |
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