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A477-0150-02 Datasheet(PDF) 1 Page - Bel Fuse Inc.

Part # A477-0150-02
Description  5 TAP LEADING EDGE CONTROL LOW VOLTAGE DELAY MODULES
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Manufacturer  BEL [Bel Fuse Inc.]
Direct Link  http://www.belfuse.com
Logo BEL - Bel Fuse Inc.

A477-0150-02 Datasheet(HTML) 1 Page - Bel Fuse Inc.

  A477-0150-02 Datasheet HTML 1Page - Bel Fuse Inc.  
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defining a degree of excellence
Corporate Office
Bel Fuse Inc.
198 Van Vorst Street, Jersey City, NJ 07302-4496
Tel: 201-432-0463
Fax: 201-432-9542
E-Mail: Belfuse@compuserve.com
Internet: http://www.belfuse.com
Specifications subject to change without notice.
Far East Office
Bel Fuse Ltd.
8F/8 Luk Hop Street
San Po Kong
Kowloon, Hong Kong
Tel: 852-2328-5515
Fax: 852-2352-3706
European Office
Bel Fuse Europe Ltd.
Preston Technology Management Centre
Marsh Lane, Preston PR1 8UD
Lancashire, U.K.
Tel: 44-1772-556601
Fax: 44-1772-888366
Cat 30-R2
Other Delays and Tolerances Available
Consult Sales
Transfer molded for better reliability
Compatible with TTL & CMOS circuits
Terminals: Electro-Tin plate phosphor bronze
Performance warranty is limited to specified parameters listed
SMD - Tape & Reel available:
32mm Wide x 16mm Pitch, 500 pieces per 13" reel
Nh Logic 1 Fanout
-
10 LSTTL Loads Max.
Nl
Logic 0 Fanout
-
10 LSTTL Loads Max.
3.0 Volts
3.0 ns (10%-90%)
1.2 x Total Delay
4 x Pulse Width
25 ma Typical
3.3 Volts
Max.
3.6
0.8
-20
20
-20
0.1
-0.5
1
-1
10
30
70o
50
Units
V
V
V
ma
ma
ma
V
V
V
ua
ua
ma
ma
C
%
%
Min.
3.0
2.4
2.9
0o
40
100 + (25000/TD) PPM/OC
300o C
Time in Minutes
for 90 Seconds Max
> 185o C
225o C Max Temp.
Infra Red
0
200o C
100o C
8
6
4
2
Vcc
Vih
Vil
Iik
Ioh
Iol
Voh
Vol
Vik
Iih
Iil
Icch
Iccl
Ta
PW
d
Tc
Supply Voltage
Logic 1 Input Voltage
Logic 0 Input Voltage
Input Clamp Current
Logic 1 Output Current
Logic 0 Output Current
Logic 1 Output Voltage
Logic 0 Output voltage
Input Clamp Voltage
Logic 1 Input Current
Logic 0 Input Current
Logic 1 Supply Current
Logic 0 Supply Current
Operating Free Air Temperature
Min. Input Pulse Width of Total Delay
Maximum Duty Cycle
Temp. Coeff. of Total Delay (TD)
Ein
Trin
PW
PP
Iccl
Vcc
Pulse Voltage
Rise Time
Pulse Width
Pulse Period
Supply Current
Supply Voltage
Input to Taps + 2 ns or 5 % , Whichever is Greater
Tap to Tap + 2 ns or 7%, Whichever is Greater
Delays measured @ 50% levels on Leading Edge only
with no loads on Taps
Rise and Fall Times measured from 10% to 90% levels
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
SMD
Thru-Hole
Total
Delay
Delay
per Tap
25 ns
30 ns
40 ns
50 ns
60 ns
70 ns
80 ns
90 ns
100 ns
125 ns
150 ns
200 ns
250 ns
5 ns
6 ns
8 ns
10 ns
12 ns
14 ns
16 ns
18 ns
20 ns
25 ns
30 ns
40 ns
50 ns
S477-0025-02
S477-0030-02
S477-0040-02
S477-0050-02
S477-0060-02
S477-0070-02
S477-0080-02
S477-0090-02
S477-0100-02
S477-0125-02
S477-0150-02
S477-0200-02
S477-0250-02
A477-0025-02
A477-0030-02
A477-0040-02
A477-0050-02
A477-0060-02
A477-0070-02
A477-0080-02
A477-0090-02
A477-0100-02
A477-0125-02
A477-0150-02
A477-0200-02
A477-0250-02
*
4o
.285 Max
.20 Max
.015 Min
.325
.23 Max
.018
.045
.80 Max
bel
(DC)
(P/N)
100o
90o
.012
.008
.22 Max
.018
.015
.80 Max
bel (DC)
(P/N)
.375
.350
.285 Max
.008
.030
.004
.012
.30
.20
.20 Typ
.10
Vcc 14
In 1
Gnd 7
12 4 10 6 8
.30
.20
.20 Typ
.10
.12 Min
Coplanarity + .002
Notes
Electrical Characteristics
Test Conditions @ 25oC
Part Numbers
Tolerances
Drive Capabilities
Recommended Temperature Profile
5 TAP LEADING EDGE CONTROL
LOW VOLTAGE DELAY MODULES
21
Rise
Time


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