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LP38856T-1.2 Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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LP38856T-1.2 Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 14 page  Application Information EXTERNAL CAPACITORS To assure regulator stability, capacitors are required on the input, output and bias pins as shown in the Typical Applica- tion Circuit. Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can be in- creased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and returned to the device ground pin with a clean analog ground. Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide sufficient capacitance over temperature. Tantalum capacitors will also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10 µF ceramic capacitor at the output will allow unlimited ca- pacitance, Tantalum and/or Aluminum, to be added in paral- lel. Input Capacitor The input capacitor must be at least 10 µF, but can be increased without limit. It’s purpose is to provide a low source impedance for the regulator input. A ceramic capaci- tor, X5R or X7R, is recommended. Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any applica- tion where the ambient temperature falls below 0˚C. Bias Capacitor The capacitor on the bias pin must be at least 1 µF. It can be any good quality capacitor (ceramic is recommended). INPUT VOLTAGE The input voltage (V IN) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. The input voltage must be at least V OUT +V DO, and no higher than whatever value is used for VBIAS. BIAS VOLTAGE The bias voltage (V BIAS) is a low current external voltage rail required to bias the control circuitry and provide gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3.0V to 5.5V to ensure proper operation of the device. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V. As the bias voltage rises above the UVLO threshold the device control circuitry become active. There is approxi- mately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity. When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the device will be functional, but the operating parameters will not be within the guaranteed limits. SUPPLY SEQUENCING There is no requirement for the order that V IN or VBIAS are applied or removed. However, the output voltage cannot be guaranteed until both V IN and VBIAS are within the range of guaranteed operating values. If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommend for this diode clamp. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when V IN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when V BIAS is below the UVLO threshold. When V BIAS is above the UVLO threshold the control cir- cuitry is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full V BIAS potential when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only by the R DS(ON) of the pass element and the output to input voltage differential. This condition is outside the guaranteed operating range and should be avoided. ENABLE OPERATION The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has an internal pull-up, through a typical 200 k Ω resistor, to V BIAS. If the Enable pin is actively driven, pulling the Enable pin above the V EN threshold of 1.25V (typical) will turn the regulator output on, while pulling the Enable pin below the V EN threshold will turn the regulator output off. There is approximately 100 mV of hysteresis built into the Enable threshold provide noise immunity. If the Enable function is not needed this pin should be left open, or connected directly to V BIAS. If the Enable pin is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while the stray capacitance is charged through the internal resistance (r EN). POWER DISSIPATION AND HEAT-SINKING A heat-sink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction tem- perature must be within the range specified under operating conditions. The total power dissipation of the device is the sum of three different points of dissipation in the device. The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula: www.national.com 10 |
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