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M29W160DT70ZA1E Datasheet(PDF) 10 Page - STMicroelectronics |
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M29W160DT70ZA1E Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 29 page  M29W160DT, M29W160DB 10/29 BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. See Tables 4 and 5, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 10, Read Mode AC Waveforms, and Table 15, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad- dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, VIH, during the whole Bus Write operation. See Figures 11 and 12, Write AC Waveforms, and Tables 16 and 17, Write AC Characteristics, for details of the timing require- ments. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data In- puts/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 14, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations un- til the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations. Additional bus opera- tions can be performed to read the Electronic Sig- nature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usu- ally used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 4 and 5, Bus Operations. Block Protection and Blocks Unprotection. Each block can be separately protected against acci- dental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotec- tion to M29 Series Flash. Table 4. Bus Operations, BYTE = VIL Note: X = VIL or VIH. Operation E G W Address Inputs DQ15A–1, A0-A19 Data Inpu ts/Outputs DQ14-DQ8 DQ7-DQ0 Bus Read VIL VIL VIH Cell Address Hi-Z Data Output Bus Write VIL VIH VIL Command Address Hi-Z Data Input Output Disable X VIH VIH X Hi-Z Hi-Z Standby VIH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL,A1 = VIL,A9 = VID, Others VIL or VIH Hi-Z 20h Read Device Code VIL VIL VIH A0 = VIH,A1 = VIL,A9 = VID, Others VIL or VIH Hi-Z C4h (M29W160DT) 49h (M29W160DB) |
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