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74LVC161 Datasheet(PDF) 2 Page - NXP Semiconductors |
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74LVC161 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 14 page Philips Semiconductors Product specification 74LVC161 Presettable synchronous 4-bit binary counter; asynchronous reset 2 1998 May 20 853-1864 19421 FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8–1A • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Asynchronous reset • Synchronous counting and loading • Two count enable inputs for n–bit cascading • Positive edge–triggered clock • Output drive capability 50 W transmission lines @85_C DESCRIPTION The 74LVC161 is a high–performance, low–power, low–voltage, Si–gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC161 is a synchronous presettable binary counter which features an internal look–head carry and can be used for high–speed counting. Synchronous operation is provided by having all flip–flops clocked simultaneously on the positive–going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive–going edge of the clock (provided that the set–up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip–flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). The look–ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set–up time, according to the following formula: fmax = 1 _______________________________ tp(max) (CP to TC) + tSU (CEP to CP) QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; TR = TF 2.5ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC CL = 50 pF VCC = 3.3V 4.9 5.7 5.2 5.7 4.5 ns fMAX maximum clock frequency 200 MHz CI input capacitance 5.0 pF CPD power dissipation capacitance per gate notes 1 and 2 39 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL x VCC2 x fo ) = sum of the outputs 2. The condition is V1 = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 16-Pin Plastic SO –40 °C to +85°C 74LVC161 D 74LVC161 D SOT109-1 16-Pin Plastic SSOP Type II –40 °C to +85°C 74LVC161 DB 74LVC161 DB SOT338-1 16-Pin Plastic TSSOP Type I –40 °C to +85°C 74LVC161 PW 74LVC161PW DH SOT403-1 |
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