Electronic Components Datasheet Search |
|
UCC2809PWTR-2 Datasheet(PDF) 5 Page - Texas Instruments |
|
UCC2809PWTR-2 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 11 page 5 UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2 The Typical Application Diagram shows an isolated flyback converter utilizing the UCC3809. Note that the capacitors CREF and CVDD are local decoupling capaci- tors for the reference and IC input voltage, respectively. Both capacitors should be low ESR and ESL ceramic, placed as close to the IC pins as possible, and returned directly to the ground pin of the chip for best stability. REF provides the internal bias to many of the IC func- tions and CREF should be at least 0.47µF to prevent REF from drooping. FB Pin The basic premise of the UCC3809 is that the voltage sense feedback signal originates from an optocoupler that is modulated by an external error amplifier located on the secondary side. This signal is summed with the current sense signal and any slope compensation at the FB pin and compared to a 1V threshold, as shown in the Typical Application Diagram. Crossing this 1V threshold resets the PWM latch and modulates the output driver on-time much like the current sense comparator used in the UC3842. In the absence of a FB signal, the output will follow the programmed maximum on-time of the os- cillator. When adding slope compensation, it is important to use a small capacitor to AC couple the oscillator waveform before summing this signal into the FB pin. By correctly selecting the emitter resistor of the optocoupler, the volt- age sense signal can force the FB node to exceed the 1V threshold when the output that is being compared ex- ceeds a desired level. Doing so drives the UCC3809 to zero percent duty cycle. Oscillator The following equation sets the oscillator frequency: () () [] FCT pF RT RT OS C =• + • + − 074 27 1 2 1 . () DRT CT pF F MAX OS C =• • + • 074 1 27 . Referring to Figure 2 and the waveforms in Figure 3, when Q1is on, CT charges via the RDS(on) of Q1 and RT1. During this charging process, the voltage of CT is sensed through RT2. The S input of the oscillator latch, S(OSC), is level sensitive, so crossing the upper thresh- old (set at 2/3 VREF or 3.33V for a typical 5.0V refer- ence) sets the Q output (CLK signal) of the oscillator latch high. A high CLK signal results in turning off Q1 and turning on Q2. CT now discharges through RT2 and the RDS(on) of Q2. CT discharges from 3.33V to the lower threshold (set at 1/3 VREF or 1.67V for a typical 5.0V reference) sensed through RT1. The R input to the oscil- lator latch, R(OSC), is also level sensitive and resets the CLK signal low when CT crosses the 1.67V threshold, turning off Q2 and turning on Q1, initiating another charg- ing cycle. Figure 3 shows the waveforms associated with the oscil- lator latch and the PWM latch (shown in the Typical Ap- plication Diagram). A high CLK signal not only initiates a discharge cycle for CT, it also turns on the internal NMOS FET on the FB pin causing any external capacitance used for leading edge blanking connected to this pin to be discharged to ground. By discharging any external capacitor completely to ground during the external switch’s off-time, the noise immunity of the converter is enhanced allowing the user to design in smaller RC com- ponents for leading edge blanking. A high CLK signal also sets the level sensitive S input of the PWM latch, S(PWM), high, resulting in a high output, Q(PWM), as shown in Figure 3. This Q(PWM) signal will remain high until a reset signal, R(PWM) is received. A high R(PWM) signal results from the FB signal crossing the 1V thresh- old, or during soft start or if the SS pin is disabled. Assuming the UVLO threshold is satisfied, the OUT sig- nal of the IC will be high as long as Q(PWM) is high and S(PWM), also referred to as CLK, is low. The OUT sig- nal will be dominated by the FB signal as long as the FB signal trips the 1V threshold while CLK is low. If the FB signal does not cross the 1V threshold while CLK is low, the OUT signal will be dominated by the maximum duty cycle programmed by the user. Figure 3 illustrates the various waveforms for a design set up for a maximum duty cycle of 70%. APPLICATION INFORMATION (cont.) + – + – SQ R Q2 Q1 3 4 RT2 CT RT1 VREF 3.33V 1.67V CLK OSC OSCILLATOR LATCH Figure 2. UCC3809 oscillator. UDG-97195 |
Similar Part No. - UCC2809PWTR-2 |
|
Similar Description - UCC2809PWTR-2 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |