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M5M467160BJ-5S Datasheet(PDF) 9 Page - Mitsubishi Electric Semiconductor |
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M5M467160BJ-5S Datasheet(HTML) 9 Page - Mitsubishi Electric Semiconductor |
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9 / 37 page  MITSUBISHI ELECTRIC Jun. 1999 FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs (Rev. 1.1) M5M467400/465400BJ,BTP -5,-6,-5S,-6S M5M467800/465800BJ,BTP -5,-6,-5S,-6S M5M465160BJ,BTP -5,-6,-5S,-6S 9 SWITCHING CHARACTERISTICS (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14) C Parameter Symbol Limits Unit M5M46X400B-5,5S M5M46X800B-5,5S M5M465160B-5,5S M5M46X400B-6,6S M5M46X800B-6,6S M5M465160B-6,6S Access time from CAS Access time from RAS Column address access time tCAC ns ns ns ns ns 15 30 35 60 13 25 30 50 tRAC tAA tCPA tOEA Access time from CAS precharge (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) Access time from OE 15 13 Min Max Min Max tOEZ (Note 12) Output disable time after OE high 15 13 ns tOFF 13 15 ns (Note 12) Output disable time after CAS high 5 5 tCLZ ns Output low impedance time from CAS low (Note 7) ~ ± Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS before RAS refresh). Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods (greater than 64 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for measuring of output signals are VOH=2.0V and VOL=0.8V. 8: Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP tCP(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT 10 A) and is not reference to VOH(min) or VOL(max). ≥ ≥ ≥ ≥ ≤ ≤ ≤ ≤ ≤ ± µ ≥ C Limits Min Max Unit Typ pF pF pF pF pF pF Input capacitance,address inputs CI (A) CI (OE) CI (RAS) CI (W) CI (CAS) CI / O Symbol Parameter Test conditions Input capacitance, OE input Input capacitance, write control input Input capacitance, RAS input Input capacitance, CAS input Input/Output capacitance, data ports 5 7 7 7 7 VI=Vss f=1MHZ Vi=25mVrms 7 CAPACITANCE (Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) ~ ± 0 0 0 0 |
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