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AT49LL080-33JC Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT49LL080-33JC Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 31 page  8 AT49LL080 3273C–FLASH–5/03 Figure 1. LPC Read Waveforms Note: 1. Field contents are valid on the rising edge of the present clock cycle. CYCTYPE + DIR ADDR TAR SYNC(3) TAR DATA CLK LFRAME LAD[3:0] START 1 2 3 4 5 6 7 8 9 10 111213 14 1516 17 1819 Table 5. LPC Read Cycle Clock Cycle Field Name Field Contents (1) LAD[3:0] LAD[3:0] Direction Comments 1 START 0000b IN LFRAME must be active (low) for the part to respond. Only the last start field (before LFRAME transitioning high) should be recognized. The START field contents indicate an LPC memory read cycle. 2 CYCTYPE + DIR 010xb IN Cycle Type: Indicates the type of cycle. Bits 3:2 must be 01 for a memory cycle. DIR: Bit 1 indicates the direction of the transfer (0 for read). Bit 0 is reserved. 3 - 10 ADDR YYYY IN These eight clock cycles make up the 32-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most significant nibble first. 11 TAR0 1111b IN then float In this clock cycle, the master (ICH) has driven the bus to all 1s and then floats the bus, prior to the next clock cycle. This is the first part of the bus “turnaround cycle”. 12 TAR1 1111b (float) Float then OUT The LPC takes control of the bus during this cycle. During the next clock cycle, it will be driving “sync data”. 13 - 14 WSYNC 0101b (WAIT) OUT The LPC outputs the value 0101, a wait-sync (WSYNC, a.k.a. “short-sync”), for two clock cycles. This value indicates to the master (ICH) that data is not yet available from the part. This number of wait- syncs is a function of the device’s access time. 15 RSYNC 0000b (READY) OUT During this clock cycle, the LPC will generate a “ready-sync” (RSYNC) indicating that the least significant nibble of the least significant byte will be available during the next clock cycle. 16 DATA YYYY OUT YYYY is the least significant nibble of the least significant data byte. 17 DATA YYYY OUT YYYY is the most significant nibble of the least significant data byte. 18 TAR0 1111b OUT then float The LPC Flash memory drives LAD0 - LAD3 to 1111b to indicate a turnaround cycle. 19 TAR1 1111b (float) Float then IN The LPC Flash memory floats its outputs, the master (ICH) takes control of LAD3 - LAD0. |
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