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M5M44800CJ-7S Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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M5M44800CJ-7S Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
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1 / 21 page  FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44800CJ,TP-5,-5S:Under development This is a family of 524288-word by 8-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for large- capacity memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. 1 DESCRIPTION APPLICATION Microcomputer memory, Refresh memory for CRT FEATURES XX=J,TP Type name access time (max.ns) RAS access time (max.ns) CAS (max.ns) access time Address time (min.ns) Cycle dissipa- (typ.mW) Power tion M5M44800CXX-7,-7S M5M44800CXX-6,-6S 60 70 15 20 30 35 110 130 375 325 15 20 access time (max.ns) OE M5M44800CXX-5,-5S 50 13 25 90 450 13 PIN DESCRIPTION Pin name A0~A9 DQ1~DQ8 RAS W Vcc Vss CAS Function Address inputs Data inputs/outputs Row address strobe input Column address strobe input Write control input Power supply (+5V) Ground (0V) Output enable input OE FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM M5M44800CJ,TP-5,-6,-7, -5S,-6S,-7S MITSUBISHI LSIs PIN CONFIGURATION (TOP VIEW) Standard 28pin SOJ, 28pin TSOP (II) Single 5V±10% supply Low stand-by power dissipation CMOS lnput level 5.5mW (Max) CMOS Input level 550µW (Max) * Operating power dissipation M5M44800Cxx-5,-5S 495mW (Max) M5M44800Cxx-6,-6S 413mW (Max) M5M44800Cxx-7,-7S 358mW (Max) Self refresh capability * Self refresh current 150µA(Max) Extended refresh capability Extended refresh current 150µA(Max) Fast page mode(1024-column random access),Read-modify-write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, CAS and OE to control output buffer impedance 1024 refresh cycles every 16.4ms (A0 ~A9) 1024 refresh cycles every 128ms (A0 ~A9) * * :Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S :option) only 18 17 1 2 3 4 5 6 (5V)VCC DQ1 DQ2 A0 A1 A2 VSS(0V) W RAS CAS OE A3 A4 A7 A6 A5 A8 21 28 DQ8 27 DQ7 26 25 19 20 Outline 28P0K(400mil SOJ) 24 23 12 11 10 9 A9 8 13 16 22 7 13 (5V)VCC 14 15 DQ3 DQ4 NC VSS(0V) DQ6 DQ5 NC 18 17 1 2 3 4 5 6 (5V)VCC DQ1 DQ2 A0 A1 A2 VSS(0V) W RAS CAS OE A3 A4 A7 A6 A5 A8 21 28 DQ8 27 DQ7 26 25 19 20 Outline 28P3Y-H(400mil TSOP Normal Bend) 24 23 12 11 10 9 A9 8 13 16 22 7 13 (5V)VCC 14 15 DQ3 DQ4 NC VSS(0V) DQ6 DQ5 NC NC:NO CONNECTION |
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