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M5M44265CTP-5S Datasheet(PDF) 5 Page - Mitsubishi Electric Semiconductor |
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M5M44265CTP-5S Datasheet(HTML) 5 Page - Mitsubishi Electric Semiconductor |
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5 / 31 page  EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs 5 Read and Refresh Cycles Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Limits Min Max Parameter Read cycle time RAS low pulse width CAS low pulse width Symbol tRC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low Read setup time before CAS low Read hold time after CAS high (Note 22) tRCH tRRH ns ns tRAL tOCH tORH RAS hold time after CAS low Read hold time after RAS high Column address to RAS hold time CAS hold time after OE low RAS hold time after OE low ns ns ns 10000 10000 10000 10000 10000 10000 0 0 90 50 8 40 13 0 25 13 13 0 0 110 60 10 48 15 0 30 15 15 0 0 130 70 13 55 20 0 35 20 20 (Note 22) M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S Limits Min Max Parameter Refresh cycle time RAS high pulse width Delay time, RAS low to CAS low Symbol tREF Unit Min Max Min Max ms ns ns ns ns ns tRP tRCD tCRP tRPC tCPN Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width (Note 20) (Note 16) (Note 17) (Note 18) ns ns ns ns ns ns tRAD tASR tASC tRAH tCAH tT Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Transition time TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Hyper-Page Mode Cycles) (Note 19) (Note 19) Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data tDZC tDZO tCDD tODD 42 35 0 30 13 50 20 5 13 15 10 10 0 0 1 0 0 20 38 30 13 50 32 25 0 40 10 50 18 5 8 13 8 8 0 0 1 0 50 20 5 10 15 0 0 0 13 13 10 10 0 1 0 0 15 15 ns ns ns ns Note 14: The timing requirements are assumed tT=2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. 17: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max). (Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted, see notes 14,15) 20 (Note 20) (Note 21) M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S 8.2 8.2 8.2 ms tREF Refresh cycle time * 128 128 128 (Note 20) Delay time, RAS high to data tRDD 13 15 ns 20 tCAL Column address to CAS hold time ns 13 18 23 |
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