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M5M4V16169DRT-10 Datasheet(PDF) 10 Page - Mitsubishi Electric Semiconductor |
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M5M4V16169DRT-10 Datasheet(HTML) 10 Page - Mitsubishi Electric Semiconductor |
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10 / 64 page  M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MITSUBISHI LSIs (REV 1.0) Jul. 1998 MITSUBISHI ELECTRIC Buffer Read Transfer & SRAM Read Buffer Write Transfer & SRAM Write Data is transferred from the Read Buffer (RB2) to the SRAM, and simultaneously, data (16 bit word) is read from the RB2 to the I/O pins. Addresses As3-9 select the SRAM Row to which the 8X16 bit block is to be written. Addresses As0-As2 decode the 16-bit word to be read. Data is first written from the I/O pins to SRAM as decoded by As0-As9. Then, the SRAM Row (=Block) decoded by As3-As9 is transferred to the Write-Buffer1 (WB1). The Buffer Write Transfer cycle "clears" all transfer mask bits in the WB1 Mask (allowing all data to be transferred in a successive DRAM Write Transfer cycle). DQCu and DQCl control Upper and Lower byte writes respectively, however all transfer mask bits in the WB1 are cleared. MODE DESCRIPTIONS (3) 10 X DQs SRAM 1KX16 8X16 8X16 8X16 8X16 8X16 16bits 16bits 16bits As3-9 1of128Decode SRAM RowDecoder DRAM 1M X 16 Ad0-11 1of4096Decode Ad3-7 1of32 Decode As0-2 1of8Decode As0-2 1of8Decode 8X16Block 8X16Block WB1 Upper Byte Lower Byte WB2 Upper Byte Lower Byte DRAM RowDecoder 16bits As0-2 1of8Decode Upper Byte Lower Byte Upper Byte Lower Byte X DQs SRAM 1KX16 8X16 8X16 8X16 8X16 8X16 16bits 16bits 16bits As3-9 1of128Decode SRAM RowDecoder DRAM 1M X 16 Ad0-11 1of4096Decode Ad3-7 1of32 Decode As0-2 1of8 Decode As0-2 1of8Decode 8X16Block 8X16Block Upper Byte Lower Byte DRAM RowDecoder 16bits As0-2 1of8Decode Upper Byte Lower Byte RB2 Upper Byte Lower Byte RB1 RB1 RB2 WB2 Upper Byte Lower Byte WB1 DQ8-15 DQ0-7 DQ8-15 DQ0-7 |
Similar Part No. - M5M4V16169DRT-10 |
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