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M5M4V4405CJ-7S Datasheet(PDF) 8 Page - Mitsubishi Electric Semiconductor |
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M5M4V4405CJ-7S Datasheet(HTML) 8 Page - Mitsubishi Electric Semiconductor |
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8 / 27 page  EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM M5M4V4405CJ,TP-6,-7,-6S,-7S MITSUBISHI LSIs Parameter Symbol Limits Unit Min Max Min Max Parameter Symbol Limits Unit Min Max Min Max Parameter Symbol Limits Unit Min Max Min Max RAS cycling, CAS= VIH tRC=min. output open Average supply current from VCC operating Average supply current from VCC refreshing Average supply current from VCC Hyper-Page-Mode Average supply current from VCC CAS before RAS refresh mode Symbol Parameter Limits Min Max Unit Typ Test conditions Test Mode Specification (Note 31) ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted) (Note 2) M5M4V4405C-6,-6S M5M4V4405C-7,-7S ICC1 (AV) (Note 3,4,5) mA 85 ICC3 (AV) ICC4(AV) ICC6(AV) (Note 3,5) (Note 3,4,5) (Note 3) mA mA mA 85 75 85 75 75 65 M5M4V4405C-6,-6S M5M4V4405C-7,-7S M5M4V4405C-6,-6S M5M4V4405C-7,-7S M5M4V4405C-6,-6S M5M4V4405C-7,-7S 75 Note 31: All previously specified electrical characteristics, switing characteristics, and timing requirements are applicable to that of test mode. SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted, see notes 6,14,15) tCAC tRAC tAA tCPA tOEA M5M4V4405C-6,-6S M5M4V4405C-7,-7S ns ns ns ns ns (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) 35 38 65 20 40 43 75 25 20 25 20 115 15 53 35 10000 65 25 135 18 60 40 10000 75 M5M4V4405C-6,-6S M5M4V4405C-7,-7S ns ns ns ns ns ns TIMING REQUIREMENTS (Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted, see notes 14,15) Read and Refresh Cycles tRAS tCAS tCSH tRSH tRAL tRC tOCH tORH ns ns 10000 10000 20 20 25 25 49 138 49 94 37 10000 94 62 166 62 112 47 10000 112 M5M4V4405C-6,-6S M5M4V4405C-7,-7S ns ns ns ns ns ns Read-Write and Read-Modify-Write Cycles ns ns 10000 10000 82 52 97 62 (Note 23) (Note 24) (Note 24) (Note 24) tRWC tRAS tCAS tCSH tRSH tCWD tRWD tAWD tCAL 23 28 ns 8 RAS, CAS cycling tRC=tWC=min. output open RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Column address to RAS hold time RAS hold time after OE low Column address to CAS hold time CAS hold time after OE low Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low |
Similar Part No. - M5M4V4405CJ-7S |
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Similar Description - M5M4V4405CJ-7S |
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