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M5M4V4405CTP-7S Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor |
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M5M4V4405CTP-7S Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor |
2 / 27 page EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM M5M4V4405CJ,TP-6,-7,-6S,-7S MITSUBISHI LSIs Row address address Column Input/Output Refresh Remark Hyper Page mode identical CAS before RAS refresh RAS-only refresh Operation FUNCTION In addition to normal read, write, and read-modify-write operations the M5M4V4405CJ,TP provide, a number of other functions, e.g., Hyper Page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1. RAS CAS OE Inputs W Input Output Table 1 Input conditions for each mode Read Write (Early write) Write (Delayed write) Read-modify-write Stand-by Hidden refresh Self refresh* ACT ACT ACT ACT ACT ACT ACT NAC ACT ACT ACT ACT NAC ACT ACT DNC NAC ACT ACT ACT DNC DNC NAC DNC ACT DNC NAC ACT DNC ACT DNC DNC APD APD APD APD APD DNC DNC DNC APD APD AP D APD DNC DNC DNC DNC OPN APD APD APD DNC OPN DNC DNC VLD OPN IVD VLD OPN VLD OPN OPN YES YES YES YES YES YES YES NO ACT ACT NAC DNC DNC DNC DNC OPN YES Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open SENSE REFRESH AMPLIFER & I /O CONTROL ROW & COLUMN ADDRESS BUFFER BLOCK DIAGRAM 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ADDRESS INPUTS VCC (3.3V) VSS (0V) OE DQ1 DQ2 DQ3 DQ4 COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT CAS RAS W A0 ~ A9 A0~ A9 CLOCK GENERATOR CIRCUIT COLUMN DECODER ROW DECODER MEMORY CELL (4,194,304 BITS) (4) DATA IN BUFFERS (4) DATA OUT BUFFERS DATA INPUTS / OUTPUTS OUTPUT ENABLE INPUT |
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