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M5M4V4265CJ-6S Datasheet(PDF) 7 Page - Mitsubishi Electric Semiconductor |
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M5M4V4265CJ-6S Datasheet(HTML) 7 Page - Mitsubishi Electric Semiconductor |
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7 / 31 page  EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M4V4265CJ,TP-5,-5S:under development 7 Limits Parameter Symbol Unit Min Max Min Max ns ns ns ns ns ns (Note 27) (Note 28) (Note 24) 16 100000 10 30 92 38 79 10 25 77 33 66 M5M4V4265C-6,-6S M5M4V4265C-7,-7S 16 100000 Note 25 : All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle. Note 26 : tHPC(min) is specified in the case of read-only and early write-only in EDO mode. Note 27 : tRAS(min) is specified as two cycles of CAS input are performed. Note 28 : tCP(max) is specified as a reference point only. Hyper page mode read/write cycle time RAS low pulse width for read or write cycle CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W low Hyper page mode read write/read modify write cycle time Hold time to maintain the data Hi-Z until CAS access OE pulse width (Hi-Z control) W pulse width (Hi-Z control) Output hold time from CAS low Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD (Note 26) EDO Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25) ns ns ns ns ns ns ns ns ns ns 42 60 57 32 50 47 60 35 38 20 50 30 33 15 5 5 7 7 7 7 7 7 Min Max 8 20 65 28 57 M5M4V4265C-5,-5S 13 100000 28 43 40 43 25 28 13 5 7 7 7 Limits Parameter CAS setup time before RAS low Symbol tCSR Unit Min Max Min Max ns ns tCHR CAS hold time after RAS low CAS before RAS Refresh Cycle (Note 29) 5 10 5 15 Note 29 : Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. M5M4V4265C-6,-6S M5M4V4265C-7,-7S ns 17 22 tCAS CAS low pulse width Min Max 5 10 M5M4V4265C-5,-5S 17 CBR self refresh RAS low pulse width tRASS µs tRPS tCHS 100 100 110 -50 130 -50 CBR self refresh RAS high precharge time CBR self refresh CAS hold time Self Refresh Cycle * (Note 30) Limits Parameter Symbol Unit Min Max Min Max ns ns M5M4V4265C-6,-6S M5M4V4265C-7,-7S 100 90 -50 Min Max M5M4V4265C-5,-5S |
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