M2V28S40ATP-7 datasheet(3/51 Pages) MITSUBISHI

Part #	M2V28S40ATP-7

Description	128M Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L

M2V28S30ATP -6,-6L,-7,-7L,-8,-8L

M2V28S40ATP -6,-6L,-7,-7L,-8,-8L

Nov. '99

MITSUBISHI LSIs

SDRAM (Rev. 1.0E)

128M Synchronous DRAM

(4-BANK x 8,388,608-WORD x 4-BIT)

(4-BANK x 4,194,304-WORD x 8-BIT)

(4-BANK x 2,097,152-WORD x 16-BIT)

MITSUBISHI ELECTRIC

3

BLOCK DIAGRAM

Type Designation Code

M2 V 28 S 3 0 A TP -8

Access Item

Package Type

Process Generation

Interface

V : LVTTL

Organization

2: x4, 3: x8, 4: x16

Synchronous DRAM

Density

28 : 128Mbit

Function

Mitsubishi DRAM

These rules are only applied to the Synchronous DRAM family.

Note : This figure shows the M2V28S30ATP.

The M2V28S20ATP configration is 4096x2048x4 of cell array and DQ 0-3.

The M2V28S40ATP configration is 4096x512x16 of cell array and DQ 0-15.

Address Buffer

A0-11

BA0,1

Control Signal Buffer

/CS

/RAS

/CAS

/WE

CLK

CKE

Clock Buffer

Control Circuitry

I/O Buffer

DQ0-7

Mode

Register

DQM

Memory Array

Bank #0

4096 x1024 x8

Cell Array

Memory Array

Bank #1

4096 x1024 x8

Cell Array

Memory Array

Bank #2

4096 x1024 x8

Cell Array

Memory Array

Bank #3

4096 x1024 x8

Cell Array

-6 : 7.5ns (PC133/3-3-3),

-7 : 10ns(PC100/2-2-2),

-8 : 10ns(PC100/3-2-2)

TP : TSOP(II)

A : 2nd. gen.

0 : Random Column

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M2V28S40ATP-7 Datasheet(PDF) 3 Page - Mitsubishi Electric Semiconductor

M2V28S40ATP-7 Datasheet(HTML) 3 Page - Mitsubishi Electric Semiconductor

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