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M2V56D30TP-10 Datasheet(PDF) 3 Page - Mitsubishi Electric Semiconductor |
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M2V56D30TP-10 Datasheet(HTML) 3 Page - Mitsubishi Electric Semiconductor |
3 / 36 page Sep.'99 Preliminary MITSUBISHI LSIs MITSUBISHI ELECTRIC DDR SDRAM (Rev.0.0) M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM 3 Type Designation Code This rule is applied to only Synchronous DRAM family. Mitsubishi Main Designation Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0 75: 133MHz@CL=2.5,100MHz@CL=2.0 Package Type TP: TSOP(II) Process Generation Function Reserved for Future Use Organization 2n 2: x4, 3: x8 DDR Synchronous DRAM Density 56: 256M bits Interface V:LVTTL, S:SSTL_3, _2 Memory Style (DRAM) M 2 S 56 D 3 0 TP - BLOCK DIAGRAM /CS /RAS /CAS /WE DM Memory Array Bank #0 DQ0 - 7 I/O Buffer Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Mode Register Control Circuitry Address Buffer A0-12 BA0,1 Clock Buffer CLK,/CLK CKE Control Signal Buffer /QFC QFC&QS Buffer DQS DLL |
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