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ST72334J Datasheet(PDF) 91 Page - STMicroelectronics |
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ST72334J Datasheet(HTML) 91 Page - STMicroelectronics |
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91 / 125 page  ST72334J/N, ST72314J/N, ST72124J 91/125 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 6.6.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the CR2 register. It is cleared by a software se- quence (an access to the SR register followed by a write to the DR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: data will not be transferred to the shift regis- ter as long as the TDRE bit is not reset. Bit 6 = TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the CR2 register. It is cleared by a software se- quence (an access to the SR register followed by a write to the DR register). 0: Transmission is not complete 1: Transmission is complete Bit 5 = RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by hardware when RE=0 or by a software sequence (an access to the SR register followed by a read to the DR register). 0: Data is not received 1: Received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is de- tected. An interrupt is generated if the ILIE=1 in the CR2 register. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Idle Line is detected 1: Idle Line is detected Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line oc- curs). This bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. Bit 3 = OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the CR2 reg- ister. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten. Bit 2 = NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR regis- ter). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. Bit 1 = FE Framing error. This bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Unused. 70 TDRE TC RDRF IDLE OR NF FE - |
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