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74LV4040N Datasheet(PDF) 8 Page - NXP Semiconductors |
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74LV4040N Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 14 page Philips Semiconductors Product specification 74LV4040 12-stage binary ripple counter 1998 Jun 23 8 AC WAVEFORMS VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VM CP INPUT Qn OUTPUT VOL VOH GND VI VM tPLH tPHL tW 1/fmax SV00322 Figure 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency MR INPUT CP INPUT VI VOH VI GND GND GND Qn OUTPUT trem tPHL tW SV00908 Figure 8. Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time TEST CIRCUIT PULSE GENERATOR RT VI D.U.T. VO CL RL = 1k VCC Test Circuit for switching times DEFINITIONS VCC VI < 2.7V VCC TEST tPLH/tPHL RT = Termination resistance should be equal to ZOUT of pulse generators. 50pF SV00901 RL = Load resistor CL = Load capacitance includes jig and probe capacitance 2.7–3.6V 2.7V Figure 9.Load circuitry for switching times |
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