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IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO

DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

INDUSTRIALTEMPERATURERANGE

Read Enable (

RENA, RENB) — When Read Enable, RENA, (RENB) is

LOW, data is read from Array A (B) to the output register on the LOW-to-HIGH

transition of the Read Clock, RCLKA (RCLKB).

When Read Enable,

RENA, (RENB) for FIFO A (B) is HIGH, the output

register holds the previous data and no new data is allowed to be loaded into

the register.

When all the data has been read from FIFO A (B), the Empty Flag,

EFA

(

EFB) will go LOW, inhibiting further read operations. Once a valid write

operation has been accomplished,

valid read can begin. The Read Enable,

RENA, (RENB)isignoredwhenFIFO

A (B) is empty.

Output Enable (

OEA, OEB) — When Output Enable, OEA (OEB) is

enabled(LOW),theparalleloutputbuffersofFIFOA(B)receivedatafromtheir

respective output register. When Output Enable,

OEA (OEB) is disabled

(HIGH), the QA (QB) output data bus is in a high-impedance state.

OUTPUTS

Full Flag (

FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write

operations, when Array A (B) is full. If no reads are performed after reset,

FFA(FFB)willgoLOWafter256writestotheIDT72V10071'sFIFOA(B),512

writes to the IDT72V11071's FIFO A (B), 1,024 writes to the IDT72V12071's

FIFO A (B), 2,048 writes to the IDT72V13071's FIFO A (B), and 4,096 writes

to the IDT72V14071's FIFO A (B).

FFA(FFB) is synchronized with respect to the LOW-to-HIGH transition of

the Write Clock WCLKA (WCLKB).

Empty Flag (

EFA, EFB) — EFA(EFB) will go LOW, inhibiting further read

operations, when the read pointer is equal to the write pointer, indicating that

Array A (B) is empty.

EFA(EFB) is synchronized with respect to the LOW-to-HIGH transition of

the Read Clock RCLKA (RCLKB).

SIGNAL DESCRIPTIONS

FIFO A and FIFO B are identical in every respect. The following description

explainstheinteractionofinputandoutputsignalsforFIFOA.Thecorrespond-

ing signal names for FIFO B are provided in parentheses.

INPUTS

CONTROLS

Reset (

RSA,RSB)—ResetofFIFOA(B)isaccomplishedwheneverRSA

(

RSB) input is taken to a LOW state. During reset, the internal read and write

pointersassociatedwiththeFIFOaresettothefirstlocation.Aresetisrequired

after power-up before a write operation can take place. The Full Flag,

FFA

(

Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is initiated

on the LOW-to-HIGH transition of WCLKA (WCLKB). Data set-up and hold

times must be met with respect to the LOW-to-HIGH transition of WCLKA

(WCLKB). The Full Flag,

FFA (FFB) is synchronized with respect to the

LOW-to-HIGH transition of the Write Clock, WCLKA (WCLKB).

The Write and Read clock can be asynchronous or coincident.

Write Enable (

WENA, WENB)— When WENA(WENB) is LOW, data can

be loaded into the input register of RAM Array A (B) on the LOW-to-HIGH

transition of every Write Clock, WCLKA (WCLKB). Data is stored in Array A

(B) sequentially and independently of any on-going read operation.

When

WENA(WENB) is HIGH, the input register holds the previous data

and no new data is allowed to be loaded into the register.

To prevent data overflow,

FFA(FFB) will go LOW, inhibiting further write

operations. Upon the completion of a valid read cycle, the

FFA (FFB) will go

WENA(WENB)isignoredwhen

FIFO A (B) is full.

Read Clock (RCLKA, RCLKB) —

Data can be read from Array A (B) on the LOW-to-HIGH transition of

RCLKA (RCLKB). The Empty Flag,

EFA(EFB) is synchronized with respect

to the LOW-to-HIGH transition of RCLKA (RCLKB).

The Write and Read Clock can be asynchronous or coincident.