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ISPLSI1016EA-100LT44 Datasheet(PDF) 8 Page - Lattice Semiconductor |
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ISPLSI1016EA-100LT44 Datasheet(HTML) 8 Page - Lattice Semiconductor |
8 / 13 page 8 Specifications ispLSI 1016EA Internal Timing Parameters1 tob 1. Internal Timing Parameters are not tested and are for reference only. Table 2-0037A/1016EA v.2.6 Outputs UNITS DESCRIPTION # PARAM. 49 Output Buffer Delay ns toen 51 I/O Cell OE to Output Enabled ns tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk) ns Global Reset Clocks tgr 59 Global Reset to GLB and I/O Registers ns todis 52 I/O Cell OE to Output Disabled ns tgy1 55 Clock Delay, Y1 to Global GLB Clock Line ns tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line ns tioy1 57 Clock Delay, Y1 to I/O Cell Global Clock Line ns tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line ns tgoe 53 Global OE ns tsl 50 Output Buffer Delay, Slew Limited Adder ns MIN. MAX. -200 — — 0.9 — 0.9 0.8 0.0 0.8 — — 0.9 3.1 0.9 0.0 3.1 0.9 1.8 0.0 1.4 5.0 -100 MIN. MIN. MAX. MAX. -125 — — 1.1 — 0.9 0.8 0.0 0.8 — — — — 2.0 5.1 1.9 5.1 1.5 1.8 0.0 2.8 3.9 5.0 5.1 — — 1.9 — 1.5 0.8 0.0 0.8 — — — 1.7 4.0 1.1 4.0 0.9 1.8 0.0 2.8 2.8 3.0 5.0 2.1 |
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