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74LV273D Datasheet(PDF) 7 Page - NXP Semiconductors |
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74LV273D Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 12 page Philips Semiconductors Product specification 74LV273 Octal D-type flip-flop with reset; positive edge-trigger 1998 May 29 7 AC WAVEFORMS VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VM VM 1/fMAX tw tPHL tPLH CP INPUT Qn OUTPUT SV00370 GND VOH VOL VI Figure 1. The clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency VM MR INPUT Qn OUTPUT tw tPHL trem CP INPUT SV00372 VI GND VI GND VOH VOL VM VM VM Figure 2. The master reset (MR) pulse width, the master reset to output (Qn) propagations delay and the master reset to clock (CP) removal time Qn OUTPUT t su t su CP INPUT Dn INPUT VM th VM VM th VI GND VI GND VOH VOL SV00371 Figure 3. Data set-up and hold times for the data input (Dn) NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUIT PULSE GENERATOR RT Vl D.U.T. VO CL RL= 1k Vcc Test Circuit for Outputs DEFINITIONS VCC VI < 2.7V 2.7–3.6V VCC 2.7V TEST tPLH/tPHL ≥ 4.5 V VCC RL = Load resistor CL = Load capacitance includes jig and probe capacitiance 50pF RT = Termination resistance should be equal to ZOUT of pulse generators. SV00902 Figure 4. Load circuitry for switching times |
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