11 / 21 page
PRELIMINARY
CY7C1305AV25
CY7C1307AV25
Document #: 38-05496 Rev. *A
Page 11 of 21
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
1.2
1.2
1.2
ns
tCHZ
tCHZ
Clock (C and C) rise to High-Z (Active to
High-Z)[21, 22]
2.5
3.0
3.0
ns
tCLZ
tCLZ
Clock (C and C) rise to Low-Z[21, 22]
1.2
1.2
1.2
ns
Notes:
19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
20. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a Read
or Write operation can be initiated.
21. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
22. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.
Switching Characteristics Over the Operating Range[19]
Cypress
Parameter
Consortium
Parameter
Description
-167
-133
-100
Unit
Min. Max. Min. Max. Min. Max.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
