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74LV138 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LV138
Description  3-to-8 line decoder/multiplexer; inverting
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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Philips Semiconductors
Product specification
74LV138
3-to-8 line decoder/demultiplexer; inverting
2
1998 Apr 28
853–1903 19290
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output capability: standard
I
CC category: MSI
DESCRIPTION
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT138.
The 74LV138 accepts three binary weighted address inputs (A0, A1,
A2) and when enabled, provide 8 mutually exclusive active LOW
outputs (Y0 to Y7).
The 74LV138 features three enable inputs: two active LOW (E1, and
E2) and one active HIGH (E3). Every output will be HIGH unless E1
and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the
74LV138 to a 1-of-32 (5 lines to 32 lines) decoder with just four
74LV138 ICs and one inverter. The 74LV138 can be used as an
eight output demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state. The 74LV138 is identical to the 74LV238
but has non-inverting (true) outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An to Yn,
E3 to Yn, En to Yn
CL = 15 pF;
VCC = 3.3 V
12
14
ns
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per
package
VCC = 3.3 V
VI = GND to VCC1
45
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°C to +125°C
74LV138 N
74LV138 N
SOT38-4
16-Pin Plastic SO
–40
°C to +125°C
74LV138 D
74LV138 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV138 DB
74LV138 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV138 PW
74LV138PW DH
SOT403-1
PIN CONFIGURATION
SV00524
1
2
3
4
5
6
7
A0
A1
A2
E1
E2
E3
Y7
VCC
Y0
Y1
Y2
Y3
Y4
Y5
14
13
12
11
10
9
GND
Y6
8
16
15
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 2, 3
A0 to A2
Address inputs
4, 5
E1 to E2
Enable inputs (active LOW)
6
E3
Enable inputs (active HIGH)
15, 14, 13, 12,
11, 10, 9, 7
Y0 to Y7
Outputs
8
GND
Ground (0 V)
16
VCC
Positive supply voltage




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