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74HCT574PW Datasheet(PDF) 7 Page - NXP Semiconductors |
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74HCT574PW Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 7 page December 1990 7 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT574 AC WAVEFORMS Fig.6 Waveforms showing the clock input (CP) pulse width, the CP input to output (Qn) propagation delays, the output transition times and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for Dn input to CP input. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. |
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