DESCRIPTION

The Hynix HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622(L)TP are a 268,435,456-bit CMOS Double

Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory

density and high bandwidth.

The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible

with SSTL_2.

FEATURES

PRELIMINARY

Rev. 0.2 / July 2003

3

HY5DU56422D(L)TP

HY5DU56822D(L)TP

HY5DU561622D(L)TP

•

All inputs and outputs are compatible with SSTL_2

interface

•

Fully differential clock inputs (CK, /CK) operation

•

Double data rate interface

•

Source synchronous - data transaction aligned to

bidirectional data strobe (DQS)

•

x16 device has two bytewide data strobes (UDQS,

LDQS) per each x8 I/O

•

Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (centered

DQ)

•

On chip DLL align DQ and DQS transition with CK

transition

•

DM mask write data-in at the both rising and falling

edges of the data strobe

•

All addresses and control inputs except data, data

strobes and data masks latched on the rising edges

of the clock

•

Programmable CAS latency 1.5, 2, 2.5 and 3

supported

•

Programmable burst length 2 / 4 / 8 with both

sequential and interleave mode

•

Internal four bank operations with single pulsed

/RAS

•

tRAS Lock-out function supported

•

Auto refresh and Self refresh supported

•

8192 refresh cycles / 64ms

•

JEDEC standard 400mil 66pin TSOP-II with 0.65mm

pin pitch (Lead free package)

•

Full and Half strength driver option controlled by

EMRS

ORDERING INFORMATION

* X means speed grade

Part No.

Configuratio

n

Package

HY5DU56422D(L)TP-X*

64Mx4

400mil

66pin

TSOP-II

(Lead-

free)

HY5DU56822D(L)TP-X*

32Mx8

HY5DU561622D(L)TP-X*

16Mx16

OPERATING FREQUENCY

Grade

CL2

CL2.5

Remark

(CL-tRCD-tRP)

- J

133MHz

166MHz

DDR333 (2.5-3-3)

- M

133MHz

133MHz

DDR266 (2-2-2)

- K

133MHz

133MHz

DDR266A (2-3-3)

- H

100MHz

133MHz

DDR266B (2.5-3-3)

- L

100MHz

125MHz

DDR200 (2-2-2)

* CL1.5 @ DDR200 supported

* CL3 supported