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LP38859S-0.8 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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LP38859S-0.8 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 14 page  Application Information (Continued) Since the V OUT rise will be exponential, not linear, the in-rush current will peak during the first time constant ( τ), and V OUT will require four additional time constants (4 τ) to reach the final value (5 τ). After achieving normal operation, should V BIAS fall below the ULVO threshold the device output will be disabled and the Soft-Start capacitor (C SS) discharge circuit will become ac- tive. The C SS discharge circuit will remain active until VBIAS falls to 500 mV (typical). When V BIAS falls below 500 mV (typical), the C SS discharge circuit will cease to function due to a lack of sufficient biasing to the control circuitry. Since V REF appears on the SS pin, any leakage through CSS will cause V REF to fall, and thus affect VOUT. A leakage of 50 nA (about 10 M Ω) through C SS will cause VOUT to be ap- proximately 0.1% lower than nominal, while a leakage of 500 nA (about 1 M Ω) will cause V OUT to be approximately 1% lower than nominal. Typical ceramic capacitors will have a factor of 10X difference in leakage between 25˚C and 85˚C, so the maximum ambient temperature must be included in the capacitor selection process. Typical C SS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 µs to 7 ms (5 τ). Values less than 1 nF can be used, but the Soft- Start effect will be minimal. Values larger than 100 nF will provide soft-start, but may not be fully discharged if V BIAS falls from the UVLVO threshold to less than 500 mV in less than 100 µs. Figure 1 shows the relationship between the C OUT value and a typical C SS value. The C SS capacitor must be connected to a clean ground path back to the device ground pin. No components, other than C SS, should be connected to the SS pin, as there could be adverse effects to V OUT. If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value is al- ways recommended. POWER DISSIPATION AND HEAT-SINKING Additional copper area for heat-sinking may be required depending on the maximum device dissipation (P D) and the maximum anticipated ambient temperature (T A) for the de- vice. Under all possible conditions, the junction temperature must be within the range specified under operating condi- tions. The total power dissipation of the device is the sum of three different points of dissipation in the device. The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula: P D(PASS) =(VIN -VOUT)xIOUT (2) The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the for- mula: P D(BIAS) =VBIAS xIGND(BIAS) (3) where I GND(BIAS) is the portion of the operating ground cur- rent of the device that is related to V BIAS. The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the for- mula: P D(IN) =VIN xIGND(IN) (4) where I GND(IN) is the portion of the operating ground current of the device that is related to V IN. The total power dissipation is then: P D =PD(PASS) +PD(BIAS) +PD(IN) (5) The maximum allowable junction temperature rise ( ∆T J) de- pends on the maximum anticipated ambient temperature (T A) for the application, and the maximum allowable operat- ing junction temperature (T J(MAX)). (6) The maximum allowable value for junction to ambient Ther- mal Resistance, θ JA, can be calculated using the formula: (7) Heat-Sinking The TO-220 Package The TO220-5 package has a θ JA rating of 60˚C/W and a θ JC rating of 3˚C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. If the needed θ JA, as calculated above, is greater than or equal to 60˚C/W then no additional heat-sinking is required since the package can safely dissipate the heat and not exceed the operating T J(MAX). If the needed θ JA is less than 60˚C/W then addi- tional heat-sinking is needed. The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θ JA will be same as shown in next section for TO-263 package. The heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, θ HA: 20131223 FIGURE 1. Typical C SS vs COUT Values www.national.com 11 |
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