HM628511HCI Series

Rev. 1, Nov. 2001, page 7 of 7

Write Cycle

HM628511HCI

-12

Parameter

Symbol

Min

Max

Unit

Notes

Write cycle time

t

WC

12

—

ns

Address valid to end of write

t

AW

8

—

ns

Chip select to end of write

t

CW

8

—

ns

9

Write pulse width

t

WP

8

—

ns

8

Address setup time

t

AS

0

—

ns

6

Write recovery time

t

WR

0

—

ns

7

Data to write time overlap

t

DW

6

—

ns

Data hold from write time

t

DH

0

—

ns

Write disable to output in low-Z

t

OW

3

—

ns

1

Output disable to output in high-Z

t

OHZ

—

6

ns

1

Write enable to output in high-Z

t

WHZ

—

6

ns

1

Notes: 1. Transition is measured

±200 mV from steady voltage with output load (B). This parameter is

sampled and not 100% tested.

2. Address should be valid prior to or coincident with

CS transition low.

3.

WE and/or CS must be high during address transition time.

4. If

CS and OE are low during this period, I/O pins are in the output state. Then, the data input

signals of opposite phase to the outputs must not be applied to them.

5. If the

CS low transition occurs simultaneously with the WE low transition or after the WE

transition, output remains a high impedance state.

6. t

7. t

8. A write occurs during the overlap of a low

CS and a low WE. A write begins at the latest

transition among

CS going low and WE going low. A write ends at the earliest transition among

CS going high and WE going high. t

write.

9. t