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ADC10DL065 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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ADC10DL065 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 26 page  DC and Logic Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V A =VD = +3.3V, VDR = +2.5V, PD = 0V, External V REF = +1.0V, fCLK = 65 MHz, fIN = 10 MHz, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel out- put mode. Boldface limits apply for T J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) I OZ TRI-STATE® Output Current V OUT = 2.5V or 3.3V 100 nA V OUT = 0V −100 nA +I SC Output Short Circuit Source Current V OUT = 0V −20 mA −I SC Output Short Circuit Sink Current V OUT =VDR 20 mA C OUT Digital Output Capacitance 5 pF POWER SUPPLY CHARACTERISTICS I A Analog Supply Current PD Pin = DGND, V REF =VA PD Pin = V D 93.7 12 111 mA (max) mA I D Digital Supply Current PD Pin = DGND PD Pin = V D ,fCLK =0 18.5 0 20.5 mA (max) mA I DR Digital Output Supply Current PD Pin = DGND, C L = 10 pF (Note 14) PD Pin = V D,fCLK =0 15 0 mA mA Total Power Consumption PD Pin = DGND, C L = 10 pF (Note 15) PD Pin = V D 370 36 434 mW (max) mW PSRR1 Power Supply Rejection Ratio Rejection of Full-Scale Error with V A =3.0V vs. 3.6V 58 dB AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V A =VD = +3.3V, VDR = +2.5V, PD = 0V, External V REF = +1.0V, fCLK = 65 MHz, fIN = 10 MHz, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel out- put mode. Boldface limits apply for T J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) f CLK1 Maximum Clock Frequency 65 MHz (min) f CLK2 Minimum Clock Frequency 15 MHz t CH Clock High Time Duty Cycle Stabilizer On 7.7 3 ns (min) t CL Clock Low Time Duty Cycle Stabilizer On 7.7 3 ns (min) t r,tf Clock Rise and Fall Times Duty Cycle Stabilizer On 2 4 ns (max) t CH Clock High Time Duty Cycle Stabilizer Off 7.7 6.2 ns (min) t CL Clock Low Time Duty Cycle Stabilizer Off 7.7 6.2 ns (min) t r,tf Clock Rise and Fall Times Duty Cycle Stabilizer Off 2 ns (max) t CONV Conversion Latency Parallel mode 7 Clock Cycles t OD Data Output Delay after Rising Clock Edge Parallel mode 5.42 3.5 ns (max) 8 ns (max) t CONV Conversion Latency Multiplex mode, Channel A 7.5 Clock Cycles t CONV Conversion Latency Multiplex mode, Channel B 8 Clock Cycles t OD Data Output Delay after Clock Edge Multiplex mode 5.54 3.5 ns (min) 8 ns (max) t SKEW ABb to Data Skew ±0.5 ns (max) t AD Aperture Delay 2 ns t AJ Aperture Jitter 1.2 ps rms t DIS Data outputs into Hi-Z Mode 10 ns www.national.com 7 |
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