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M68AW256ML70ZH1T Datasheet(PDF) 4 Page - STMicroelectronics |
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M68AW256ML70ZH1T Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 23 page M68AW256M 4/23 SUMMARY DESCRIPTION The M68AW256M is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 262,144 words by 16 bits. The device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an au- tomatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW256 is available in TFBGA48 (6x8mm - 6x8 active ball array, 0.75mm pitch), TFBGA48 (7x8mm - 6x8 active ball array, 0.75 mm pitch) and in TSOP44 Type II packages. In addition to the standard version, both packages are also available in Lead-free version, in compli- ance with the JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free solder- ing processes. Figure 2. Logic Diagram Table 1. Signal Names AI04870b 18 A0-A17 W DQ0-DQ15 VCC M68AW256M G 16 E UB LB VSS A0-A17 Address Inputs DQ0-DQ15 Data Input/Output E Chip Enable G Output Enable W Write Enable UB Upper Byte Enable Input LB Lower Byte Enable Input VCC Supply Voltage VSS Ground NC Not Connected Internally DU Don’t Use as Internally Connected |
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