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AS7C1026A-15BC Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation |
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AS7C1026A-15BC Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation |
6 / 9 page AS7C1026A AS7C31026A ® 2/6/01 Alliance Semiconductor P. 6 of 9 Data retention characteristics (over the operating range) Data retention waveform AC test conditions Notes 1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, and C. 4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ± 500 mV from steady-state voltage. 5 This parameter is guaranteed, but not tested. 6WE is High for read cycle. 7CE and OE are Low for read cycle. 8 Address valid prior to or coincident with CE transition Low. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. 11 All write cycle timings are referenced from the last valid address to the first transitioning address. 12 Not applicable. 13 C=30pF, except all high Z and low Z parameters where C=5pF. Parameter Symbol Test conditions Min Max Unit VCC for data retention VDR VCC = 2.0V CE ≥ V CC–0.2V VIN ≥ VCC–0.2V or VIN ≤ 0.2V 2.0 – V Data retention current ICCDR –1 ma Chip deselect to data retention time tCDR 0– ns Operation recovery time tR tRC –ns Input leakage current |ILI|– 1 µA VCC CE tR tCDR Data retention mode VCC VCC VDR ≥ 2.0V VIH VIH VDR 255W C(14) 320W GND +3.3V Figure C: 3.3V Output load 168W Thevenin Equivalent: DOUT +1.728V (5V and 3.3V) 255W C(14) 480W GND +5V Figure B: 5V Output load 10% 90% 10% 90% GND +3.0V Figure A: Input pulse 2 ns DOUT DOUT – Output load: see Figure B or Figure C. – Input pulse level: GND to 3.0V. See Figure A. – Input rise and fall times: 2 ns. See Figure A. – Input and output timing reference levels: 1.5V. |
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