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EP224 Datasheet(PDF) 5 Page - Altera Corporation |
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EP224 Datasheet(HTML) 5 Page - Altera Corporation |
5 / 16 page Altera Corporation 5 EP220 & EP224 Classic EPLDs The XOR gate can implement active-high or active-low logic, and can use DeMorgan’s inversion to reduce the number of product terms needed to implement a function. If the EP220 and EP224 register outputs do not require an OE signal, the internal product term can hold the output in an enabled state; if a global OE signal is required, any input can be dedicated to the task, and all eight product terms can be programmed accordingly. High-Frequency, Low-Skew Global Clock EP220 and EP224 devices have extremely low output-pin skew: registered output skew (tOCR) is typically less than 300 ps; combinatorial output skew (tOSC) is typically less than 400 ps. This low output-skew rate makes EP220 and EP224 devices ideal for high-frequency system Clock applications, including Intel Pentium microprocessors, 486-based PCs, and PCI bus designs. PLD Compatibility The EP220 and EP224 devices are a logical superset of most high-speed, 24-pin PAL/GAL devices. Industry-standard JEDEC Files from compatible devices can be programmed into EP220 or EP224 devices. Table 1 summarizes some of the devices that can be replaced or upgraded with EP220 and EP224 devices. Table 1. EP220- and EP224-Compatible Devices (Part 1 of 4) PAL/GAL Vendor PAL/GAL Device Altera Replacement Device Speed Grade Advanced Micro Devices PAL16L8 EP220-7 -7 PAL16R8 PALCE16V8 PAL20L8 EP224-7 PAL20R8 PALCE20V8 PAL16L8 EP220-10 -10 PAL16R8 PALCE16V8 PAL20L8 EP224-10 PAL20R8 PALCE20V8 |
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