9

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WE512K16-XG4X

April 1999

Rev. 2

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

LOAD DATA AAAA

TO

ADDRESS 5555

LOAD DATA 5555

TO

ADDRESS 2AAA

LOAD DATA 8080

TO

ADDRESS 5555

LOAD DATA AAAA

TO

ADDRESS 5555

LOAD DATA 5555

TO

ADDRESS 2AAA

LOAD DATA 2020

TO

ADDRESS 5555

LOAD DATA XXXX

TO

LOAD LAST WORD

TO

LAST ADDRESS

FIGURE 9 –

SOFTWARE BLOCK DATA PROTECTION

NOTES:

2. Write Protect state will be activated at end of write even if no other

data is loaded.

3. Write Protect state will be deactivated at end of write period even if

no other data is loaded.

4. 1 to 128 words of data may loaded.

EXIT DATA

SOFTWARE DATA PROTECTION

A software write protection feature may be enabled

or disabled by the user. When shipped by White

Microelectronics, the module has the feature disabled.

Write access to the device is unrestricted.

To enable software write protection, the user writes three

access code words to three special internal locations.

Once write protection has been enabled, each write to the

EEPROM must use the same three-word write sequence

to permit writing. After setting software data protection,

any attempt to write to the device without the three-word

command sequence will start the internal write timers. No

data will be written to the device, however, for the duration

a six-word write sequence of specific data to specific

locations. Power transitions will not reset the software

write protection.

Each 128K-word block of the EEPROM has independent

write protection. One or more blocks may be enabled and

the rest disabled in any combination. The software write

protection guards against inadvertent writes during power

transitions, or unauthorized modification using a PROM

programmer.

HARDWARE DATA PROTECTION

These features protect against inadvertent writes to the

module. These are included to improve reliability during

normal operation:

a)

5 msec typical before allowing write cycles.

b)

While below 3.8V typical write cycles are inhibited.

c)

Write inhibiting

Holding OE# low and either CS# or WE# high

inhibits write cycles.

d)

Noise filter

Pulses of <8ns (typ) on WE# or CS# will not initiate

a write cycle.