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WE512K16-150G4QA Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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WE512K16-150G4QA Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
5 / 10 page 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE512K16-XG4X April 1999 Rev. 2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. ADDRESS CS# OE# OUTPUT READ The module stores data at the memory location determined by the address pins. When CS# and OE# are low and WE# is high, this data is present on the outputs. When CS# and OE# are high, the outputs are in a high impedance state. This two line control prevents bus contention. Notes: OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - toe after an address change without impact on tACC. CS1-4# are used as bank selects. During reads, only one CSx# can be active at one time. AC READ CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol -140 -150 -200 Unit Min Max Min Max Min Max Read Cycle Time trc 140 150 200 ns Address Access Time tacc 140 150 200 ns Chip Select Access Time tacs 140 150 200 ns Output Hold from Address Change, OE# or CS# toh 0 0 0 ns Output Enable to Output Valid toe 0 50 0 55 0 55 ns Chip Select or OE# to High Z Output tdf 50 70 70 ns FIGURE 5 – READ WAVEFORMS |
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