PRELIMINARY
CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Document #: 38-05489 Rev. *A
Page 10 of 24
Write Cycle Descriptions (CY7C1510V18 and CY7C1512V18) [2, 8]
BWS0/NWS0
BWS1 / NWS1
KK
Comments
L
L
L-H
–
During the Data portion of a Write sequence
:
CY7C1510V18
− both nibbles (D[7:0]) are written into the device,
CY7C1512V18
− both bytes (D[17:0]) are written into the device.
L
L
–
L-H During the Data portion of a Write sequence
:
CY7C1510V18
− both nibbles (D[7:0]) are written into the device,
CY7C1512V18
− both bytes (D[17:0]) are written into the device.
L
H
L-H
–
During the Data portion of a Write sequence
:
CY7C1510V18
− only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1512V18
− only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
L
H
–
L-H During the Data portion of a Write sequence
:
CY7C1510V18
− only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1512V18
− only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
H
L
L-H
–
During the Data portion of a Write sequence
:
CY7C1510V18
− only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1512V18
− only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
H
L
–
L-H During the Data portion of a Write sequence
:
CY7C1510V18
− only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1512V18
− only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
H
H
L-H
–
No data is written into the devices during this portion of a write operation.
H
H
–
L-H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions (CY7C1514V18) [2, 8]
BWS0 BWS1 BWS2 BWS3
KK
Comments
L
L
L
L
L-H
-
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
L
L
L
-
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
H
H
H
L-H
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L
H
H
H
-
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
H
L
H
H
L-H
-
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
Notes:
1. The above application shows four QDRII being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
↑represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0,NWS1,BWS0 ,BWS1,BWS2 and BWS3 can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
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