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LTC2444C Datasheet(PDF) 10 Page - Linear Technology |
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LTC2444C Datasheet(HTML) 10 Page - Linear Technology |
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10 / 28 page  LTC2444/LTC2445/ LTC2448/LTC2449 10 sn2444589 2444589fs SERIAL INTERFACE PINS The LTC2444/LTC2445/LTC2448/LTC2449 transmit the conversion results and receive the start of conversion command through a synchronous 3- or 4-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result and program the speed, resolution and input channel. Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 38) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2444/LTC2445/LTC2448/LTC2449 cre- ate their own serial clock. In the External SCK mode of operation, the SCK pin is used as input. The internal or first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN– pins is maintained within the – 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from –FS = –0.5 • VREF to +FS = 0.5 • VREF. For differential input voltages greater than +FS, the conversion result is clamped to the value corre- sponding to the +FS + 1LSB. For differential input voltages below –FS, the conversion result is clamped to the value corresponding to –FS – 1LSB. Table 2. LTC2444/LTC2445/LTC2448/LTC2449 Output Data Format Differential Input Voltage Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 … Bit 0 VIN* EOC DMY SIG MSB VIN* ≥ 0.5 • VREF** 0 0110 0 0 … 0 0.5 • VREF** – 1LSB 0 0101 1 1 … 1 0.25 • VREF** 0 0101 0 0 … 0 0.25 • VREF** – 1LSB 0 0100 1 1 … 1 0 0 0100 0 0 … 0 –1LSB 0 0011 1 1 … 1 – 0.25 • VREF** 0 0011 0 0 … 0 – 0.25 • VREF** – 1LSB 0 0010 1 1 … 1 – 0.5 • VREF** 0 0010 0 0 … 0 VIN* < –0.5 • VREF** 0 0001 1 1 … 1 *The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–. APPLICATIO S I FOR ATIO MSB BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0 LSB Hi-Z 2444 F04 SIG BIT 29 “0” BIT 30 EOC Hi-Z CS SCK SDI SDO BUSY BIT 31 1 0 EN SGL A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOX ODD 12345 6 7 89 10 11 12 13 14 32 Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing |
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