CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A
Page 5 of 24
AC Test Loads and Waveforms[8, 9, 10, 11, 12]
Switching Characteristics Over the Operating Range[13]
Parameter
Description
7C451-12
7C453-12
7C454-12
7C451-14
7C453-14
7C454-14
7C451-20
7C453-20
7C454-20
7C451-30
7C453-30
7C454-30
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tCKW
Write Clock Cycle
12
14
20
30
ns
tCKR
Read Clock Cycle
12
14
20
30
ns
tCKH
Clock HIGH
5
6.5
9
12
ns
tCKL
Clock LOW
5
6.5
9
12
ns
tA
[14]
Data Access Time
9
10
15
20
ns
tOH
Previous Output Data Hold After Read HIGH
0
0
0
0
ns
tFH
Previous Flag Hold After Read/Write HIGH
0
0
0
0
ns
tSD
Data Set-Up
4
5
6
7
ns
tHD
Data Hold
0
0
0
0
ns
tSEN
Enable Set-Up
4
5
6
7
ns
tHEN
Enable Hold
0
0
0
0
ns
tOE
OE LOW to Output Data Valid
9
10
15
20
ns
tOLZ
[7,15]
OE LOW to Output Data in Low Z
0
0
0
0
ns
tOHZ
[7,15]
OE HIGH to Output Data in High Z
9
10
15
20
ns
tPG
Read HIGH to Parity Generation
9
10
15
20
ns
tPE
Read HIGH to Parity Error Flag
9
10
15
20
ns
tFD
Flag Delay
9
10
15
20
ns
tSKEW1
[16]
Opposite Clock After Clock
0
0
0
0
ns
Notes:
8.
CL = 30 pF for all AC parameters except for tOHZ.
9.
CL = 5 pF for tOHZ.
10. All AC measurements are referenced to 1.5V except tOE, tOLZ, and tOHZ.
11.
tOE and tOLZ are measured at ± 100 mV from the steady state.
12. tOHZ is measured at +500 mV from VOL and – 500 mV from VOH.
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms
and capacitance as in notes 8 and 9, unless otherwise specified.
14. Access time includes all data outputs switching simultaneously.
15. At any given temperature and voltage condition, tOLZ is greater than tOHZ for any given device.
16. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes
of flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the opposite clock in the current
clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost
Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the
clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
3.0V
5V
OUTPUT
R1500
Ω
R2
333
Ω
CL
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<3 ns
<3 ns
OUTPUT
2V
Equivalent to:
THÉVENIN EQUIVALENT
C451-4
200
Ω
ALL INPUT PULSES
C451-5