FLASH MEMORY

K8S6415ET(B)B

Revision 1.1

January, 2006

11

DEVICE OPERATION

The device has I/Os that accept both address and data information. To write a command or command sequence (which includes pro-

The device provide the unlock bypass mode to save its program time for program operation. Unlike the standard program command

sequence which is comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass

mode. One block, multiple blocks, or the entire device can be erased. Table 3 indicates the address space that each block occupies.

The device’s address space is divided into sixteen banks: Bank 0 contains the boot/parameter blocks, and the other banks(from Bank

1 to 15) consist of uniform blocks. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “block address”

for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

Read Mode

The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in

asynchronous mode. After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset com-

mand is required to return a bank to the read(or erase-suspend-read)mode if DQ5 goes high during an active program/erase opera-

tion, or if the bank is in the autoselect mode.

The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. That

means device enters burst read mode from asynchronous read mode to burst read mode using CLK and AVD signal. When the burst

read is finished(or terminated), the device return to asynchronous read mode automatically.

Asynchronous Read Mode

For the asynchronous read mode a valid address should be asserted on A/DQ0-A/DQ15 and A16-A21, while driving AVD and CE to

into sixteen banks, each bank remains enabled for read access until the command register contents are altered.

OE to valid data at the output. The asynchronous access time is measured from a valid address, falling edge of AVD or falling edge

of CE whichever occurs last. To prevent the memory content from spurious altering during power transition, the initial state machine

is set for reading array data upon device power-up, or after a hardware reset.

Synchronous (Burst) Read Mode

The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the sys-

ation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further

details. The status data also can be read during burst read mode by using AVD signal with a bank address. To initiate the synchro-

nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed

the program or erase operation.

Continuous Linear Burst Read

The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. Note that

internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is cross-

ing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of addtional

clock cycle can vary from zero to three cycles, and the exact number of additional clock cycle depends on the starting address of

burst read.(Refer to Figure 13) The RDY output indicates this condition to the system by pulsing low. The device will continue to out-

put sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the

system asserts CE high, RESET low or AVD low in conjunction with a new address.(See Table 4.) The reset command does not ter-

minate the burst read operation.

If the host system crosses the bank boundary while reading in burst mode, and the accessed bank is not programming or erasing, a

additional clock cycles are needed as previously mentioned. If the host system crosses the bank boundary while the accessed bank

is programming or erasing, that is busy bank, the synchronous read will be terminated.