EM6635

03/03 REV. B

Copyright

 2002, EM Microelectronic-Marin SA

11

www.emmicroelectronic.com

The port P1 has several special functions assigned to its inputs:

8.1.1 Edge Detector

The port input P10 and P11 have edge detectors connected to the corresponding debouncer outputs. Both edge detectors

create output signals of 488us at positive and negative edges. Each edge detector pulse from P10 or P11 input creates a

pulse "M", which is the clock input for the event counter. Every change at P10 or P11 creates an "M" pulse.

Also, an interrupt "M" is generated by this signal

The P13 input is logically combined as "AND" with P22 and P23 input, then input into a debouncer, whose output creates an

Input Reset if enabled.

8.1.2 Input Interrupt

The port P12 input (after debouncer) is connected to an edge detector, active at positive and negative edges. Its 488us

output signal creates an interrupt P12 in register INT-Stat-2 (bit 0, address H66).

The port P13 input (after debouncer) is connected to an edge detector, active at positive and negative edges. Its 488us

output signal creates an interrupt P13 in register INT-Stat-2 (bit 1, address H66).

8.1.3 Input Pull Down

Each P1 input has associated pulldown transistors. These NMOS transistors are activated with a 512Hz signal with the

duration of 31us (OP-6A) or 62us (OP-6B). A "0" input level is additionally hold by the circuitry shown in fig.8:

512HzPD_Control

to Port Logic

P1

Fig.9: Port P1, P2 Input Pull Down

The pull down elements at port 1 can globally be disactivated by mask option OP-7B.

Note: Extra pull down transistors are active at this port during the CPURES signal.

CPU Access Format:

Register

Add Hex

Add Dec

bit3

bit2

bit1

bit0

Config2

45

69

W

R

(DisInpRes)

(DisInpRes)

(P5DebOn)

(P5DebOn)

(P2DebOn)

(P2DebOn)

P1DebOn

P1DebOn

Port P1

47

71

R

P13

P12

P11

P10

8.2 Input Port 2

The port P2 is a 4bits input port used to read the terminal logic levels P20 to P23 into the CPU.

The port is equipped with 4 debouncers, which can be enabled by signal "P2DebOn" commonly for all 4 inputs. With

debouncers active, any input level must be present glitchfree for at least the debouncer time tDEB =1.95ms, to be

transferred to the debouncer output, which can be read by the CPU.

When "P2DebOn" is at "0" level, the port P2 input is directly passed to the debouncer outputs.

Port 2 Interrupt:

Each debouncer output of port 2 is connected to the input of a positive edge dedector. The 4 edge detector outputs are

logically combined as OR to create the P2 interrupt signal INT-P2 (bit 1, address H68).

In this way, any valid positive transition at P2 input can create an interrupt if not masked.

The P22 and P23 inputs are combined logically as "AND" with P13 input and applied to a debouncer. The debounced signal

can create an Input Reset if not disabled by "DisInpRes".

Each P2 input has associated pull down transistors. These NMOS transistors are activated with a 512 Hz signal with the

duration of 31µs (OP-6A) or 62µs (OP-6B). A "0" input level is additionally hold by the circuitry shown in Fig. 8.

The pull down elements at port P2 can globally be disactivated by mask option OP-14B.

Note: Extra pull down transistors are active at this port during the CPURES signal.

CPU Access Format:

Register

Add Hex

Add Dec

bit3

bit2

bit1

bit0

Config2

45

69

W

R

DisInpRes

DisInpRes

(P5DebOn)

(P5DebOn)

P2DebOn

P2DebOn

(P1DebOn)

(P1DebOn)

Port 2

48

72

R

P23

P22

P21

P20