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U2730B-BFSG1 Datasheet(PDF) 4 Page - TEMIC Semiconductors |
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U2730B-BFSG1 Datasheet(HTML) 4 Page - TEMIC Semiconductors |
4 / 12 page U2730B-B Rev. A1, 22-Jul-98 Preliminary Information 4 (12) Reference Divider Four different scaling factors of the reference divider can be selected by the input Pin S: 32, 35, 36, 48. Starting from a reference oscillator frequency of 16.384 MHz/ 17.92 MHz/ 18.432 MHz/ 24.576 MHz these scaling factors result in an output frequency of the reference divider of 512 kHz. If the input control Pin C is left open (high-impedance state), a test signal which monitors the output frequency of the reference divider appears at the output Pin TRD of the test interface. LO Divider The LO divider is operated at the fixed division ratio 2464. Assuming the settings described in the section ‘Reference divider’, the oscillator’s frequency is controlled to be 1261.568 MHz in locked state, the output frequency of the RF divider is 512 kHz. In analogy to the reference divider, a test signal which monitors the output frequency of the RF divider appears at the output Pin TMD of the test interface if the input control Pin C is left open (high-impedance state). Phase Comparator, Charge Pump and Loop Filter The tristate phase detector causes the charge pump to source or to sink current at the output Pin PD depending on the phase relation of its input signals which are provided by the reference and the RF divider respectively. By means of the control Pin C, two different values of this current can be selected, and furthermore the charge-pump current can be switched off. A high-gain amplifier (output Pin CD) which is implemented to construct a loop filter, as shown in the application circuit, can be switched off by means of the control Pin C. In the application circuit figure 3, the loop filter is completed by connecting the Pins PD and CD by an appropriate RC network. An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If a phase lock is detected, the open collector output Pin PLCK is set to HIGH. It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the voltage at the control Pin C is chosen to be half the supply voltage, or if this control pin is left open, the lock-detector function is de-activated and the logical value of the PLCK output is undefined. Absolute Maximum Ratings Parameters Symbol Value Unit Supply voltage Pins 3, 9, 20 and 28 VCC –0.3 to +9.5 V RF input voltage Pins 25 and 26 VRF 750 mVpp Voltage at Pin AGC Pin 18 VAGC 0.5 to 6 V Voltage at Pin TH Pin 17 VTH –0.3 to +4.0 V Input voltage at Pin TANK (internal oscillator overdriven) Pin 5 VTANK 1 Vpp Current at IF output Pin 19 IIF 4.0 mA Reference input voltage (diff.) Pins 15 and 16 REF, NREF 1 Vpp Control input voltage Pins 1, 2 and 27 C, S –0.3 to +9.5 V PLCK output current Pin 14 IPLCK 0.5 mA PLCK output voltage Pin 14 VPLCK –0.3 to +5.5 V Junction temperature Tj 125 °C Storage temperature Tstg –40 to +125 °C Operating Range Parameters Symbol Min. Typ. Max. Unit Supply voltage Pins 3, 9, 20 and 28 VCC 8.0 8.5 9.35 V Ambient temperature Tamb –40 +85 °C |
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