200pin DDR SDRAM SODIMM

M470L1714BT0

Rev. 0.1 June. 2001

Typical case: VDD = 2.5V, T = 25’C

Worst case : VDD = 2.7V, T = 10’C

Conditions

Symbol

Typical

Worst

Operating current - One bank Active-Precharge;

tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

DQ,DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

IDD0

-

-

Operating current - One bank operation ; One bank open, BL=4, Reads

- Refer to the following page for detailed test condition

IDD1

-

-

Percharge power-down standby current; All banks idle; power - down mode;

CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Vin = Vref for DQ,DQS and DM

IDD2P

-

-

Precharge Floating standby current; CS# > =VIH(min);All banks idle;

CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Address and other control inputs changing once per clock cycle;

Vin = Vref for DQ,DQS and DM

IDD2F

-

-

Precharge Quiet standby current; CS# > = VIH(min); All banks idle;

CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);

Vin = Vref for DQ ,DQS and DM

IDD2Q

-

-

Active power - down standby current ; one bank active; power-down mode;

CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Vin = Vref for DQ,DQS and DM

IDD3P

-

-

Active standby current; CS# >= VIH(min); CKE>=VIH(min);

one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,

133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice

per clock cycle; address and other control inputs changing once

per clock cycle

IDD3N

-

-

Operating current - burst read; Burst length = 2; reads; continguous burst;

One bank active; address and control inputs changing once per clock cycle;

CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =

133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A

IDD4R

-

-

Operating current - burst write; Burst length = 2; writes; continuous burst;

One bank active address and control inputs changing once per clock cycle;

CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,

CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice

per clock cycle, 50% of input data changing at every burst

IDD4W

-

-

Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh

IDD5

-

-

Self refresh current; CKE =< 0.2V; External clock should be on;

tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B

IDD6

-

-

Orerating current - Four bank operation ; Four bank interleaving with BL=4

-Refer to the following page for detailed test condition

IDD7A

-

-

DDR SDRAM SPEC Items and Test Conditions