8

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WV3EG232M64STSU-D4

September 2005

Rev. 1

PRELIMINARY

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Parameter

Symbol

Conditions

DDR333 @

CL = 2.5 Max

Unit

Operating current

- One bank Active-

Precharge

DQ,DM and DQS inputs changing twice per clock cycle; address and control

inputs changing once per clock cycle

404

mA

Operating current

- One bank operation

One bank open, BL=4, Reads - Refer to the following page for detailed test

condition

416

mA

Percharge power-

down standby current

DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM

40

mA

Precharge Floating

standby current

133Mhz for DDR266A & DDR266B; Address and other control inputs

200

mA

Active power - down

standby current

DM

88

mA

Active standby

current

DQ, DQS and DM inputs changing twice per clock cycle; address and other

control inputs changing once per clock cycle

360

mA

Operating current

- burst read

Burst length = 2; reads; continguous burst; One bank active; address and

DDR266B ; 50% of data changing at every burst; lout = 0mA

436

mA

Operating current

- burst write

Burst length = 2; writes; continuous burst; One bank active address and

DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of

input data changing at every burst

488

mA

Auto refresh current

DDR266B at 133Mhz; distributed refresh

1544

mA

Self refresh current;

CKE =< 0.2V

DDR266A & DDR266B

40

mA

Orerating current

- Four bank operation

Four bank interleaving with BL=4 -Refer to the following page for detailed test

condition

1248

mA

NOTE:

** Value calculated as all module ranks in this operation condition.