WV3EG128M72EFSR335D3MG datasheet(5/13 Pages) WEDC

Part #	WV3EG128M72EFSR335D3MG

Description	1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA

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Manufacturer	WEDC [White Electronic Designs Corporation]

Direct Link	http://www.whiteedc.com

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

March 2005

Rev. 0

ADVANCED

WV3EG128M72EFSR-D3

IDD SPECIFICATIONS AND TEST CONDITIONS

Recommended operating conditions, 0°C

≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V

Includes DDR SDRAM component only

Parameter

Symbol

Conditions

DDR333@

CL=2.5

Max

DDR266@

CL=2

Max

DDR266@

CL=2.5

Max

Units

Operating Current

IDD0

One device bank; Active - Precharge; tRC=tRC (MIN);

tCK=tCK (MIN); DQ,DM and DQS inputs changing once

per clock cycle; Address and control inputs changing

once every two cycles.

4140

mA

Operating Current

IDD1

One device bank; Active-Read-Precharge Burst = 2;

tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and

control inputs changing once per clock cycle.

4680

mA

Precharge Power-

Down Standby Current

IDD2P

All device banks idle; Power-down mode; tCK=tCK (MIN);

CKE=(low)

180

rnA

Idle Standby Current

IDD2F

CS# = High; All device banks idle; tCK=tCK (MIN); CKE

= high; Address and other control inputs changing once

per clock cycle. VIN = VREF for DQ, DQS and DM.

1620

mA

Active Power-Down

Standby Current

IDD3P

One device bank active; Power-Down mode; tCK (MIN);

CKE=(low)

1260

mA

Active Standby Current

IDD3N

CS# = High; CKE = High; One device bank; Active-

Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and

DQS inputs changing twice per clock cycle; Address

and other control inputs changing once per clock cycle.

1800

mA

Operating Current

IDD4R

Burst = 2; Reads; Continuous burst; One device bank

active; Address and control inputs changing once per

clock cycle; TCK= TCK (MIN); lOUT = 0mA.

4770

mA

Operating Current

IDD4W

Burst = 2; Writes; Continuous burst; One device bank

active; Address and control inputs changing once per

clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs

changing once per clock cycle.

4590

rnA

Auto Refresh Current

IDD5

tRC = tRC (MIN)

7020

mA

Self Refresh Current

IDD6

CKE

≤ 0.2V

180

mA

Operating Current

IDD7A

Four bank interleaving Reads (BL=4) with auto

precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address

and control inputs change only during Active Read or

Write commands.

9090

9000

mA

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