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WV3DG64127V10D2 Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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WV3DG64127V10D2 Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 8 page 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG64127V-D2 April 2005 Rev. 0 White Electronic Designs Corp. reserves the right to change products or specifications without notice. ADVANCED* OPERATING AC PARAMETERS VCC, VCCQ = +3.3v ±0.3V, 0°C - 70°C Parameter Symbol 775 10 Unit Note Min Max Min Max Min Max CLK cycle time CAS latency=3 tCC 7.5 1000 7.5 1000 10 1000 ns 1 CAS latency=2 7.5 10 10 CLK to valid output delay CAS latency=3 tSAC 5.4 5.4 6 ns 1, 2 CAS latency=2 5.4 6 6 Output data hold time CAS latency=3 tOH 333 ns 2 CAS latency=2 3 3 3 CLK high pulse width tCH 2.5 2.5 3 ns 3 CLK low pulse width tCL 2.5 2.5 3 ns 3 Input setup time tSS 1.5 1.5 2 ns 3 Input hold time tSH 0.8 0.8 1 ns 3 CLK to output in Low-Z tSLZ 111 ns 2 CLK to outpu in Hi-Z CAS latency=3 tSHZ 5.4 5.4 6 ns CAS latency=2 5.4 6 6 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. |
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