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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WEDPY256K72V-XBX

August 2004

Rev. 7

NOTES:

1. Q(A4) refers to output from addrss A4. Q(A4 + 1) refers to output from the next internal burst address to following A4.

2. CS2# and CS2 have timing identical to CS1#. On this diagram, when CS1# is LOW, CS2# is LOW and CS2# is HIGH.

When CS1# is HIGH, CS2 is HIGH and CS2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed.

4. GW# is HIGH.

5. Back-to back READs may be controlled by either ADSP# or ADSC#.

CLK

A1

A2

A3

A4

(NOTE 1)

High-Z

High-Z

Back-to-Back READs

(Note 5)

Single WRITE

Burst Read

Back-to-Back

WRITEs

A5

A6

Don’t care

Undefined

ADSP#

ADSC#

Address

BWE#, BWa#-BWd#

(Note 4)

CS#

(Note 2)

ADV#

OE#

D

Q#

Q(A1)

Q(A2)

D(A2)

Q(A4+2)

Q(A4+3)

Q(A4)

D(A6)

D(A5)

Q

(A4+1)