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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WEDPY256K72V-XBX

August 2004

Rev. 7

TRUTH TABLE

Operation

Address Used

CS1

CS2

CS2

ZZ

ADSP

ADSC

ADV

WRITE

OE

CLK

DQ

Deselected Cycle, Power-Down

None

H

X

X

L

X

L

X

X

X

L-H

HIGH Z

Deselected Cycle, Power-Down

None

L

X

L

L

L

XXXX

L-H

HIGH Z

Deselected Cycle, Power-Down

None

L

H

X

L

L

XXXX

L-H

HIGH Z

Deselected Cycle, Power-Down

None

L

X

L

L

H

L

X

X

X

L-H

HIGH Z

Deselected Cycle, Power-Down

None

L

H

X

L

H

L

X

X

X

L-H

HIGH Z

SNOOZE MODE, Power-Down

None

X

X

X

H

XXXXXX

HIGH Z

READ Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

L

L-H

Q

READ Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

H

L-H

HIGH Z

WRITE Cycle, Begin Burst

External

L

L

H

L

H

L

X

L

X

L-H

D

READ Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

L

L-H

Q

READ Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

H

L-H

HIGH Z

READ Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L-H

Q

READ Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L-H

HIGH Z

READ Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L-H

Q

READ Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L-H

HIGH Z

WRITE Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L-H

D

WRITE Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L-H

D

READ Cycle, Suspend Burst

Current

X

X

X

L

HHHH

L

L-H

Q

READ Cycle, Suspend Burst

Current

X

X

X

L

HHHHH

L-H

HIGH Z

READ Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

H

Q

READ Cycle, Suspend Burst

Current

H

X

X

L

X

HHHH

L-H

HIGH Z

WRITE Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L-H

D

WRITE Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L-H

D

NOTE:

1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW.

2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or WE#) are LOW or GW# is

LOW. WRITE# = H for all BWx#, BWE#, GW# High.

3. BWa enables WRITEs to DQ0-8. BWb# enables WRITEs to DQ9-17. BWc enables WRITEs to DQ18-26. BWd# enables

WRITE to DQ27-35.

4. All inputs excepts OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending bursts.

6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH

throughout the input data hold time.

7. This device contains circuitry that will ensure the outputs will be held in High-Z during power-up.

8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more

byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing

diagram for clarification.