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WEDPN16M64VR-125B2C Datasheet(PDF) 7 Page - White Electronic Designs Corporation |
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WEDPN16M64VR-125B2C Datasheet(HTML) 7 Page - White Electronic Designs Corporation |
7 / 15 page WEDPN16M64VR-XB2X 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs January 2005 Rev. 0 COMMANDS The Truth Table provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/ next state information. INPUTS OUTPUT OE# LE# CLK A Y H XXX Z LL X L L LL X H H LH I L L LH I H H L H L or H X Y0(1) NOTES: 1. Output level before the indicated steady-state input conditions were established. REGISTER FUNCTION TABLE COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0-11. See Mode Register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. TRUTH TABLE — COMMANDS AND DQM OPERATION (NOTE 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR I/Os COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) ( 3) L L H H X Bank/Row X READ (Select bank and column, and start READ burst) (4) L H L H L/H 8 Bank/Col X WRITE (Select bank and column, and start WRITE burst) (4) L H L L L/H 8 Bank/Col Valid BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L X Code X AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X X X LOAD MODE REGISTER (2) L L L L X Op-Code X Write Enable/Output Enable (8) – – – – L – Active Write Inhibit/Output High-Z (8) – – – – H – High-Z NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-11 define the op-code written to the Mode Register. 3. A0-12 provide row address, and BA0, BA1 determine which bank is made active. 4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay). |
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